Data Sheet AD532
Rev. E | Page 9 of 14
FUNCTIONAL DESCRIPTION
The functional block diagram for the AD532 is shown in Figure 1
and the complete schematic in Figure 13. In the multiplying and
squaring modes, Z is connected to the output to close the feedback
around the output op amp. In the divide mode, it is used as an
input terminal.
The X and Y inputs are fed to high impedance differential
amplifiers featuring low distortion and good common-mode
rejection. The amplifier voltage offsets are actively laser trimmed to
zero during production.
The product of the two inputs is resolved in the multiplier cell
using Gilberts linearized transconductance technique. The cell
is laser trimmed to obtain V
OUT
= (X
1
− X
2
)(Y
1
− Y
2
)/10 V. The
built in op amp is used to obtain low output impedance and make
possible self contained operation. The residual output voltage offset
can be zeroed at V
OS
in critical applications. Otherwise, the V
OS
pin
should be grounded.
X
2
X
1
Y
1
COM
R2
R34
R9
R1
Q1
Q2
Q3 Q4
Q5
Q6
R3
R6 R8 R16
Q7
Q8
Q14Q15
Q9
Q10
R13
Y
2
R18
R4
R5
R10
R32
Q28
Q11
Q12
R11
R19
R14
R12
R15
Q13
Q16 Q17
R23
R20
R22
R21
C1
Q21
R27
Q25
Z
R33
V
OS
OUTPUT
R30
R28
R29
R31
Q26
Q27
Q22
Q23
Q24
R26
R25R24
Q20
Q19
Q18
+V
S
–V
S
CAN
00502-004
Figure 13. Schematic Diagram
AD532 Data Sheet
Rev. E | Page 10 of 14
AD532 PERFORMANCE CHARACTERISTICS
Multiplication accuracy is defined in terms of total error at 25°C
with the rated power supply. The value specified is in percent of
full scale and includes X
IN
and Y
IN
nonlinearities, feedback and
scale factor error. To this must be added such application
dependent error terms as power supply rejection, common-
mode rejection and temperature coefficients (although worst
case error over temperature is specified for the AD532S). Total
expected error is the rms sum of the individual components
because they are uncorrelated.
Accuracy in the divide mode is only a little more complex. To
achieve division, the multiplier cell must be connected in the
feedback of the output op amp as shown in Figure 16. In this
configuration, the multiplier cell varies the closed-loop gain of
the op amp in an inverse relationship to the denominator voltage.
Therefore, as the denominator is reduced, output offset, bandwidth,
and other multiplier cell errors are adversely affected. The divide
error and drift are then ε
m
× 10 V/(X
1
− X
2
), where ε
m
represents
multiplier full-scale error and drift and (X
1
− X
2
) is the absolute
value of the denominator.
NONLINEARITY
Nonlinearity is easily measured in percent harmonic distortion.
The curves of Figure 5 and Figure 6 characterize output distortion
as a function of input signal level and frequency respectively,
with one input held at plus or minus 10 V dc. In Figure 6, the
sine wave amplitude is 20 V p-p.
AC FEEDTHROUGH
AC feedthrough is a measure of the multiplier’s zero suppression.
With one input at zero, the multiplier output should be zero
regardless of the signal applied to the other input. Feedthrough
as a function of frequency for the AD532 is shown in Figure 7.
It is measured for the condition V
X
= 0, V
Y
= 20 V p-p and V
Y
= 0,
V
X
= 20 V (p-p) over the given frequency range. It consists
primarily of the second harmonic and is measured in millivolts
peak-to-peak.
COMMON-MODE REJECTION
The AD532 features differential X and Y inputs to enhance its
flexibility as a computational multiplier/divider. Common-mode
rejection for both inputs as a function of frequency is shown in
Figure 8. It is measured with X
1
= X
2
= 20 V p-p, (Y
1
Y
2
) = 10 V
dc and Y
1
= Y
2
= 20 V p-p, (X
1
− X
2
) = 10 V dc.
DYNAMIC CHARACTERISTICS
The closed-loop frequency response of the AD532 in the multiplier
mode typically exhibits a 3 dB bandwidth of 1 MHz and rolls off
at 6 dB/octave, thereafter. Response through all inputs is essentially
the same as shown in Figure 9. In the divide mode, the closed-
loop frequency response is a function of the absolute value of
the denominator voltage as shown in Figure 10.
Stable operation is maintained with capacitive loads to 1000 pF
in all modes, except the square root for which 50 pF is a safe
upper limit. Higher capacitive loads can be driven if a 100 Ω
resistor is connected in series with the output for isolation.
POWER SUPPLY CONSIDERATIONS
Although the AD532 is tested and specified with ±15 V dc
supplies, the device may be operated at any supply voltage from
±10 V to ±18 V for the J and K versions, and ±10 V to ±22 V
for the S version. The input and output signals must be reduced
proportionately to prevent saturation; however, with supply
voltages below ±15 V, as shown in Figure 11. Because power
supply sensitivity is not dependent on external null networks as
in other conventionally nulled multipliers, the power supply
rejection ratios are improved from 3 to 40 times in the AD532
.
NOISE CHARACTERISTICS
The AD532 is sampled to assure that output noise will have no
appreciable effect on accuracy. Typical spot noise vs. frequency
is shown in Figure 12.
Data Sheet AD532
Rev. E | Page 11 of 14
APPLICATIONS
The performance and ease of use of the AD532 is achieved through
the laser trimming of thin film resistors deposited directly on
the monolithic chip. This trimming on the chip technique provides
a number of significant advantages in terms of cost, reliability,
and flexibility over conventional in package trimming of off the
chip resistors mounted or deposited on a hybrid substrate.
Trimming on the chip eliminates the need for a hybrid substrate
and the additional bonding wires that are required between the
resistors and the multiplier chip. By trimming more appropriate
resistors on the AD532 chip itself, the second input terminals
that were committed to external trimming networks have been
freed to allow fully differential operation at both the X and Y
inputs. Further, the requirement for an input attenuator to
adjust the gain at the Y input has been eliminated, letting the
user take full advantage of the high input impedance properties
of the input differential amplifiers. Therefore, the AD532 offers
greater flexibility for both algebraic computation and transducer
instrumentation applications.
Provision for fine trimming the output voltage offset has been
included. This connection is optional, however, as the AD532 has
been factory trimmed for total performance as described in the
listed specifications.
REPLACING OTHER IC MULTIPLIERS
Existing designs using IC multipliers that require external
trimming networks can be simplified using the pin for pin
replaceability of the AD532 by merely grounding the X
2
, Y
2
,
and V
OS
terminals. The V
OS
terminal must always be grounded
when unused.
Multiplication
Z
OUT
AD532
X
1
X
2
Y
1
Y
2
V
OUT
V
OS
20k
+V
S
–V
S
V
OUT
=
(X
1
– X
2
) (Y
1
– Y
2
)
10V
(OPTIONAL)
00502-013
Figure 14. Multiplier Connection
For operation as a multiplier, the AD532 must be connected as
shown in Figure 14. The inputs can be fed differentially to the X
and Y inputs or single-ended by simply grounding the unused
input. Connect the inputs according to the desired polarity in
the output. The Z terminal is tied to the output to close the
feedback loop around the op amp (see Figure 1). The offset adjust
V
OS
is optional and is adjusted when both inputs are zero volts
to obtain zero out, or to null other system offsets.
Squaring
AD532
X
1
X
2
Y
1
Y
2
V
OUT
20k
+V
S
–V
S
+V
S
–V
S
V
OS
V
OUT
=
V
IN
2
10V
(OPTIONAL)
Z
OUT
V
IN
00502-014
Figure 15. Squarer Connection
The squaring circuit in Figure 15 is a simple variation of the
multiplier. The differential input capability of the AD532, however,
can obtain a positive or negative output response to the input, a
useful feature for control applications, as it might eliminate the
need for an additional inverter somewhere else.
Division
AD532
20k
(X
0
)
47k
2.2k
10k
1k
(SF)
+V
S
–V
S
+V
S
–V
S
V
OUT
=
10VZ
X
Z
OUT
Z
V
OUT
X
X
1
X
2
Y
1
Y
2
00502-015
Figure 16. Divider Connection
The AD532 can be configured as a two-quadrant divider by
connecting the multiplier cell in the feedback loop of the op
amp and using the Z terminal as a signal input, as shown in
Figure 16. It should be noted, however, that the output error is
given approximately by 10 V ε
m
/(X
1
− X
2
), where ε
m
is the total
error specification for the multiply mode and bandwidth by f
m
×
(X
1
− X
2
)/10 V, where f
m
is the bandwidth of the multiplier.
Further, to avoid positive feedback, the X input is restricted to
negative values. Thus, for single-ended negative inputs (0 V to
−10 V), connect the input to X and the offset null to X
2
; for single-
ended positive inputs (0 V to +10 V), connect the input to X
2
and the offset null to X
1
. For optimum performance, gain (SF)
and offset (X
0
) adjustments are recommended as shown and
explained in Table 5.
For practical reasons, the useful range in denominator input is
approximately 500 mV ≤ |(X
1
− X
2
)| ≤ 10 V. The voltage offset
adjust (V
OS
), if used, is trimmed with Z at zero and (X
1
− X
2
) at
full scale.

AD532JDZ

Mfr. #:
Manufacturer:
Analog Devices Inc.
Description:
Special Purpose Amplifiers MLTIPLIER/DIVIDER IC
Lifecycle:
New from this manufacturer.
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