MAX5120/MAX5121
(MAX5120) and Figure 3b (MAX5121) to achieve these
adjustments. Connect a 33nF capacitor from REFADJ
to AGND to establish low-noise operation of the DAC.
Larger capacitor values may be used, but will result in
increased start-up delay. The time constant (τ) for the
start-up delay is determined by the REFADJ input
impedance of 4kΩ and C
REFADJ
:
τ = 4kΩ · C
REFADJ
External Reference
An external reference may be applied to the REF pin.
Disable the internal reference by pulling REFADJ to
V
DD
. This allows an external reference signal (AC- or
DC-based) to be fed into the REF pin. For proper oper-
ation, do not exceed the input voltage range limits of
0V to (V
DD
- 1.4V) for V
REF
.
Determine the output voltage using the following equa-
tion (REFADJ = V
DD
; OS = AGND):
V
OUT
= [V
REF
· (NB / 4096)] · 1.6384V/V
where NB is the numeric value of the MAX5120/
MAX5121 input code (0 to 4095), V
REF
is the external
reference voltage, and 1.6384V/V is the gain of the
internal output amplifier. The REF pin has a minimum
input resistance of 40kΩ and is code-dependent.
Output Amplifier
The output amplifier of the MAX5120/MAX5121
employs a trimmed resistor-divider to set a gain of
+1.6384V/V and minimize the gain error. With its on-
board laser-trimmed +1.25V reference and the output
buffer gain, the MAX5121 achieves a full-scale output
of +2.0475V, while the MAX5120 provides a +4.095V
full-scale output with a +2.5V reference.
The output amplifier has a typical slew rate of 0.6V/µs
and settles to ±0.5LSB within 20µs, with a load of 5kΩ
in parallel with 100pF. Loads less than 1kΩ may result
in degraded performance.
The OS pin may be used to adjust the output offset volt-
age. For instance, to achieve a +1V offset, apply
-1.566V (Offset = -[Output Buffer Gain - 1] · V
OS
) to OS
to produce an output voltage range from +1V to (1V +
V
REF
· 1.6384V/V). Note that the DAC’s output range is
still limited by the maximum output voltage specifica-
tion.
Power-Down Mode
The MAX5120/MAX5121 feature software- and hard-
ware-programmable (PD pin) shutdown modes that
reduce the typical supply current to 3µA. To enter soft-
ware shutdown mode, program the control sequence
for the DAC as shown in Table 1.
In shutdown mode, the amplifier output becomes high
impedance and the serial interface remains active.
Data in the input registers is saved, allowing the
MAX5120/MAX5121 to recall the output state prior to
entering shutdown when returning to normal operation
mode. To exit shutdown mode, load both input and
DAC registers simultaneously or update the DAC regis-
ter from the input register. When returning from shut-
down mode, wait 2ms for the reference to settle. When
using an external reference, the DAC requires only
20µs for the output to stabilize.
+3V/+5V, 12-Bit, Serial Voltage-Output DACs
with Internal Reference
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