MAX5120BEEE Datasheet MAX5121AEEE, MAX5120AEEE, MAX5121BEEE | P13-P15

Serial Data Output

The contents of the internal shift register are output

serially on DOUT, which allows for daisy-chaining (see

Applications Information

) of multiple devices as well as

data readback. The MAX5120/MAX5121 may be pro-

grammed to shift data out on DOUT on the serial

clock’s rising edge (Mode 1) or falling edge (Mode 0).

The latter is the default during power-up and provides a

lag of 16 clock cycles, maintaining SPI, QSPI,

MICROWIRE, and PIC16/PIC17 compatibility. In Mode

1, the output data lags DIN by 15.5 clock cycles.

During power-down, DOUT retains its last digital state

prior to shutdown.

User-Programmable Output (UPO)

The UPO feature allows an external device to be con-

trolled through the serial-interface setup (Table 1),

thereby reducing the number of microcontroller I/O

ports required. During power-down, this output will

retain the last digital state before shutdown. With CLR

pulled low, UPO will reset to the default state after wake

up.

MAX5120/MAX5121

+3V/+5V, 12-Bit, Serial Voltage-Output DACs

with Internal Reference

______________________________________________________________________________________ 13

Table 3. Detailed SSPCON Register Contents

Receive Overflow Detection BitXSSPOV BIT6

BIT7

Clock Polarity Select Bit. CKP = 0 for SPI master-mode selection.0CKP BIT4

BIT5

Synchronous Serial Port Enable Bit.

0: Disables serial port and configures these pins as I/O port pins.

1: Enables serial port and configures SCK, SDO, and SCI as serial-

port pins.

1SSPEN

0SSPM2 BIT2

BIT3

1SSPM0 BIT0

BIT1

CONTROL BIT

0SSPM1

Write Collision Detection BitXWCOL

SYNCHRONOUS SERIAL-PORT CONTROL REGISTER

(SSPCON)

MAX5120/MAX5121

SETTINGS

Synchronous Serial Port Mode Select Bit. Sets SPI master mode

and selects f

CLK

= f

OSC

/ 16.

0SSPM3

= Don’t care

Table 4. Detailed SSPSTAT Register Contents

= Don’t care

SPI Clock Edge Select Bit. Data will be transmitted on the rising

edge of the serial clock.

1CKE BIT6

Buffer Full Status Bit

BIT7

Update Address

Read/Write Bit Information

Stop BitXP BIT4

BIT5 Data Address BitXD/A

XR/W BIT2

BIT3

XBF BIT0

BIT1

CONTROL BIT

XUA

SPI Data Input Sample Phase. Input data is sampled at the mid-

dle of the data output time.

0SMP

SYNCHRONOUS SERIAL-PORT CONTROL REGISTER

(SSPSTAT)

MAX5120/MAX5121

SETTINGS

Start BitXS

MAX5120/MAX5121

__________Applications Information

Definitions

Integral Nonlinearity (INL)

Integral nonlinearity (Figure 8a) is the deviation of the

values on an actual transfer function from a straight

line. This straight line can be either a best-straight-line

fit (closest approximation to the actual transfer curve)

or a line drawn between the endpoints of the transfer

function, once offset and gain errors have been nulli-

fied. For a DAC, the deviations are measured at every

single step.

Differential Nonlinearity (DNL)

Differential nonlinearity (Figure 8b) is the difference

between an actual step height and the ideal value of

1LSB. If the magnitude of the DNL is less than 1LSB, the

DAC guarantees no missing codes and is monotonic.

Offset Error

The offset error (Figure 8c) is the difference between

the ideal and the actual offset point. For a DAC, the off-

set point is the step value when the digital input is zero.

This error affects all codes by the same amount and

can usually be compensated for by trimming.

Gain Error

Gain error (Figure 8d) is the difference between the

ideal and the actual full-scale output voltage on the

transfer curve, after nullifying the offset error. This error

alters the slope of the transfer function and corre-

sponds to the same percentage error in each step.

+3V/+5V, 12-Bit, Serial Voltage-Output DACs

with Internal Reference

14 ______________________________________________________________________________________

000 010001 011 100 101 110

AT STEP

011 (1/2 LSB )

AT STEP

001 (1/4 LSB )

111

DIGITAL INPUT CODE

ANALOG OUTPUT VALUE (LSB)

Figure 8a. Integral Nonlinearity

Figure 8b. Differential Nonlinearity

000 010001 011 100 101

DIFFERENTIAL LINEARITY

ERROR (-1/4 LSB)

DIFFERENTIAL

LINEARITY ERROR (+1/4 LSB)

1 LSB

DIGITAL INPUT CODE

ANALOG OUTPUT VALUE (LSB)

000 010001 011

ACTUAL

DIAGRAM

IDEAL DIAGRAM

ACTUAL

OFFSET

POINT

OFFSET ERROR

(+1 1/4 LSB)

IDEAL OFFSET

POINT

DIGITAL INPUT CODE

ANALOG OUTPUT VALUE (LSB)

Figure 8c. Offset Error

Figure 8d. Gain Error

000 101100 110 111

IDEAL DIAGRAM

GAIN ERROR

(-1 1/4 LSB)

IDEAL FULL-SCALE OUTPUT

ACTUAL

FULL-SCALE

OUTPUT

DIGITAL INPUT CODE

ANALOG OUTPUT VALUE (LSB)

Settling Time

The settling time is the amount of time required from the

start of a transition until the DAC output settles to its new

output value within the converter’s specified accuracy.

Digital Feedthrough

Digital feedthrough is noise generated on the DAC’s

output when any digital input transitions. Proper board

layout and grounding will significantly reduce this

noise, but there will always be some feedthrough

caused by the DAC itself.

Unipolar Output

Figure 9 shows the MAX5120/MAX5121 setup for

unipolar, Rail-to-Rail

operation with a gain of

1.6384V/V. With its +2.5V internal reference, the

MAX5120 can generate a unipolar output range of 0V

to +4.095V. The MAX5121 produces a range of 0V to

+2.0475V with its on-board +1.25V reference. Table 5

lists example codes for unipolar output voltages. An off-

set to the output voltage can be achieved by simply

connecting the appropriate voltage to the OS pin, as

shown in Figure 10.

Bipolar Output

The MAX5120/MAX5121 can be configured for unity-

gain bipolar operation (OS = OUT) using the circuit

shown in Figure 11. The output voltage V

OUT

is thereby

given by the following equation:

OUT

= V

REF

· [ {G · (NB / 4096)} - 1]

where NB is the numeric value of the DAC’s binary

input code, V

REF

is the voltage of the internal (or exter-

nal) precision reference, and G is the overall gain. The

application circuit in Figure 11 uses a low-cost opera-

tional amplifier (MAX4162) external to the MAX5120/

MAX5121 in a unity-gain configuration. This provides

an overall circuit gain of 2V/V. Table 6 lists example

codes for bipolar output voltages.

Reset (RSTVAL) and Clear (

CLR

) Functions

The MAX5120/MAX5121 DACs offer a clear pin (CLR)

that resets the output to a certain value, depending

upon how RSTVAL is set. RSTVAL = DGND sets the

output to 0, and RSTVAL = V

sets the output to mid-

scale when CLR is pulled low.

The CLR pin has a minimum input resistance of 40kΩ in

series with a diode to the supply voltage (V

). If the

digital voltage is higher than the supply voltage for the

part, a small input current may flow, but this current will

be limited to (V

CLR

- V

- 0.5V) / 40kΩ.

Note: Clearing the DAC will also cause the part to exit

software shutdown (PD = 0).

MAX5120/MAX5121

+3V/+5V, 12-Bit, Serial Voltage-Output DACs

with Internal Reference

______________________________________________________________________________________ 15

MAX5120

MAX5121

DAC

GAIN = 1.638V/V

REF

OUT

DGNDAGND

+5V/+3V

0.6384R

Figure 9. Unipolar Output Circuit (OS = AGND) Using Internal

(1.25V/2.5V) or External Reference. With external reference,

pull REFADJ to V

MAX5120

MAX5121

DAC

AGND DGND

REF

REFADJ

OUT

+5V/+3V

0.6384R

Figure 10. Circuit for Adding Offset to the DAC’s Output

AGNDDGND

MAX5120

MAX5121

DAC

REF

OUT

50k 50k

V-

V+

OUT

+5V/+3V

0.6384R

MAX4162

Figure 11. Unity-Gain Bipolar Output Circuit Using Internal

(+1.25V/+2.5V) or External Reference. With external reference,

pull REFADJ to V

Rail-to-Rail is a registered trademark of Nippon Motorola, Ltd.

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P20

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