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MC100LVEL32DG

P1-P3P4-P6P7-P8
© Semiconductor Components Industries, LLC, 2016
July, 2016 − Rev. 11
1 Publication Order Number:
MC100LVEL32/D
MC100LVEL32
3.3 V ECL ÷2 Divider
Description
The MC100LVEL32 is an integrated ÷2 divider. The LVEL32 is
functionally identical to the EL32, but operates from a 3.3 V supply.
The reset pin is asynchronous and is asserted on the rising edge.
Upon power-up, the internal flip-flop will attain a random state; the
reset allows for the synchronization of multiple LVEL32’s in a system.
The V
BB
pin, an internally generated voltage supply, is available to
this device only. For single-ended input conditions, the unused
differential input is connected to V
BB
as a switching reference voltage.
V
BB
may also rebias AC coupled inputs. When used, decouple V
BB
and V
CC
via a 0.01 mF capacitor and limit current sourcing or sinking
to 0.5 mA. When not used, V
BB
should be left open.
Features
• 510 ps Propagation Delay
• 2.6 GHz Typical Maximum Frequency
• ESD Protection:
♦ > 4 KV Human Body Model
♦ > 200 V Machine Model
• The 100 Series Contains Temperature Compensation
• PECL Mode Operating Range:
V
CC
= 3.0 V to 3.8 V with V
EE
= 0 V
• NECL Mode Operating Range:
V
CC
= 0 V with V
EE
= −3.0 V to −3.8 V
• Internal Input Pulldown Resistors
• Meets or Exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
• Moisture Sensitivity:
♦ Level 1 for SOIC−8
♦ Level 3 for TSSOP−8
♦ Level 1 for DFN−8
♦ For Additional Information, see Application Note AND8003/D
• Flammability Rating: UL 94 V−0 @ 0.125 in,
Oxygen Index: 28 to 34
• Transistor Count = 111 Devices
• These Devices are Pb-Free, Halogen Free and are RoHS Compliant
*For additional marking information, refer to
Application Note AND8002/D
.
MARKING DIAGRAMS*
KV32
ALYWG
G
SOIC−8 NB
D SUFFIX
CASE 751−07
1
8
TSSOP−8
DT SUFFIX
CASE 948R−02
1
8
1
8
www.onsemi.com
KVL32
ALYW
G
1
8
DFN−8
MN SUFFIX
CASE 506AA
4E M G
G
14
(Note: Microdot may be in either location)
A = Assembly Location
L = Wafer Lot
Y = Year
W = Work Week
M
= Date Code
G = Pb-Free Package
SOIC−8 NB TSSOP−8 DFN−8
ORDERING INFORMATION
Device Package Shipping†
MC100LVEL32DG SOIC−8 NB
(Pb-Free)
98 Units / Tube
MC100LVEL32DR2G
2500 Tape & Reel
TSSOP−8
(Pb-Free)
MC100LVEL32DTR2G 2500 Tape & Reel
TSSOP−8
(Pb-Free)
MC100LVEL32DTG 100 Units / Tube
DFN−8
(Pb-Free)
MC100LVEL32MNR4G 1000 Tape & Reel
†For information on tape and reel specifications, in-
cluding part orientation and tape sizes, please refer
to our Tape and Reel Packaging Specifications
Brochure, BRD8011/D
.
SOIC−8 NB
(Pb-Free)
MC100LVEL32
www.onsemi.com
2
4
3
Figure 1. Logic Diagram and Pinout Assessment
1
2
5
6
7
8
Q
V
EE
V
CC
QCLK
V
BB
R
÷2
Reset
CLK
Table 1. PIN DESCRIPTION
Pin Function
CLK*, CLK**
Q, Q
Reset*
V
BB
V
CC
V
EE
EP
ECL Differential Clock Inputs
ECL Differential Data ÷2
Outputs
ECL Asynch Reset
Reference Voltage Output
Positive Supply
Negative Supply
(DFN8 only) Thermal exposed pad
must be connected to a sufficient ther-
mal conduit. Electrically connect to the
most negative supply (GND) or leave
unconnected, floating open.
*Pin will default low when left open, per internal 75 K pull-down to
V
EE
.
** Pin will default to V
CC
/2 when left open per internal 75 KW pull-
down to V
EE
and 75 KW pull-up to V
CC
.
Table 2. MAXIMUM RATINGS
Symbol Parameter Condition 1 Condition 2 Rating Unit
V
CC
PECL Mode Power Supply V
EE
= 0 V 8 to 0 V
V
EE
NECL Mode Power Supply V
CC
= 0 V −8 to 0 V
V
I
PECL Mode Input Voltage
NECL Mode Input Voltage
V
EE
= 0 V
V
CC
= 0 V
V
I
≤ V
CC
V
I
≥ V
EE
6 to 0
−6 to 0
V
V
I
PECL Mode Input Voltage
NECL Mode Input Voltage
V
EE
= 0 V
V
CC
= 0 V
V
I
≤ V
CC
V
I
≥ V
EE
6 to 0
−6 to 0
V
I
out
Output Current Continuous
Surge
50
100
mA
I
BB
V
BB
Sink/Source ±0.5 mA
T
A
Operating Temperature Range −40 to +85 °C
T
stg
Storage Temperature Range −65 to +150 °C
q
JA
Thermal Resistance (Junction-to-Ambient) 0 lfpm
500 lfpm
SOIC−8 NB
SOIC−8 NB
190
130
°C/W
q
JC
Thermal Resistance (Junction-to-Case) Standard Board SOIC−8 NB 41 to 44 ±5% °C/W
q
JA
Thermal Resistance (Junction-to-Ambient) 0 lfpm
500 lfpm
TSSOP−8
TSSOP−8
185
140
°C/W
q
JC
Thermal Resistance (Junction-to-Case) Standard Board TSSOP−8 41 to 44 ±5% °C/W
q
JA
Thermal Resistance (Junction-to-Ambient) 0 lfpm
500 lfpm
DFN−8
DFN−8
129
84
°C/W
T
sol
Wave Solder (Pb-Free) < 2 to 3 sec @ 260°C 265 °C
q
JC
Thermal Resistance (Junction-to-Case) (Note 1) DFN−8 35 to 40 °C/W
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. JEDEC standard multilayer board − 2S2P (2 signal, 2 power)
MC100LVEL32
www.onsemi.com
3
Table 3. LVPECL DC CHARACTERISTICS (V
CC
= 3.3 V; V
EE
= 0.0 V (Note 1))
Symbol
Characteristic
−40°C 25°C 85°C
Unit
Min Typ Max Min Typ Max Min Typ Max
I
EE
Power Supply Current 29 35 29 35 31 36 mA
V
OH
Output HIGH Voltage (Note 2) 2215 2295 2420 2275 2345 2420 2275 2345 2420 mV
V
OL
Output LOW Voltage (Note 2) 1470 1605 1745 1490 1595 1680 1490 1595 1680 mV
V
IH
Input HIGH Voltage (Single-Ended) 2135 2420 2135 2420 2135 2420 mV
V
IL
Input LOW Voltage (Single-Ended) 1490 1825 1490 1825 1490 1825 mV
V
BB
Output Voltage Reference 1.92 2.04 1.92 2.04 1.92 2.04 V
V
IHCMR
Input HIGH Voltage Common Mode
Range (Differential Configuration) (Note 3)
V
PP
< 500 mV
V
PP
≥ 500 mV
1.2
1.4
3.1
3.1
1.1
1.3
3.1
3.1
1.1
1.3
3.1
3.1
V
I
IH
Input HIGH Current 150 150 150
mA
I
IL
Input LOW Current
CLK
CLK
0.5
−600
0.5
−600
0.5
−600
mA
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
1. Input and output parameters vary 1:1 with V
CC
. V
EE
can vary ±0.3 V.
2. Outputs are terminated through a 50 W resistor to V
CC
− 2.0 V.
3. V
IHCMR
min varies 1:1 with V
EE
, max varies 1:1 with V
CC
. The V
IHCMR
range is referenced to the most positive side of the differential input signal.
Normal operation is obtained if the HIGH level falls within the specified range and the peak-to-peak voltage lies between V
PP
min and 1 V.
Table 4. LVNECL DC CHARACTERISTICS (V
CC
= 0.0 V; V
EE
= −3.3 V (Note 1))
Symbol
Characteristic
−40°C 25°C 85°C
Unit
Min Typ Max Min Typ Max Min Typ Max
I
EE
Power Supply Current 29 35 29 35 31 36 mA
V
OH
Output HIGH Voltage (Note 2) −1085 −1005 −880 −1025 −955 −880 −1025 −955 −880 mV
V
OL
Output LOW Voltage (Note 2) −1830 −1695 −1555 −1810 −1705 −1620 −1810 −1705 −1620 mV
V
IH
Input HIGH Voltage (Single-Ended) −1165 −880 −1165 −880 −1165 −880 mV
V
IL
Input LOW Voltage (Single-Ended) −1810 −1475 −1810 −1475 −1810 −1475 mV
V
BB
Output Voltage Reference −1.38 −1.26 −1.38 −1.26 −1.38 −1.26 V
V
IHCMR
Input HIGH Voltage Common Mode
Range (Differential Configuration)
(Note 3)
V
PP
< 500 mV
V
PP
≥ 500 mV
−2.1
−1.9
−0.2
−0.2
−2.1
−1.9
−0.2
−0.2
−2.1
−1.9
−0.2
−0.2
V
I
IH
Input HIGH Current 150 150 150
mA
I
IL
Input LOW Current
CLK
CLK
0.5
−600
0.5
−600
0.5
−600
mA
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
1. Input and output parameters vary 1:1 with V
CC
. V
EE
can vary ±0.3 V.
2. Outputs are terminated through a 50 W resistor to V
CC
− 2.0 V.
3. V
IHCMR
min varies 1:1 with V
EE
, max varies 1:1 with V
CC
. The V
IHCMR
range is referenced to the most positive side of the differential input signal.
Normal operation is obtained if the HIGH level falls within the specified range and the peak-to-peak voltage lies between V
PP
min and 1 V.
P1-P3P4-P6P7-P8

MC100LVEL32DG

Mfr. #:
Buy MC100LVEL32DG
Manufacturer:
ON Semiconductor
Description:
Clock Drivers & Distribution 3.3V ECL Divide By 2 Divider
Lifecycle:
New from this manufacturer.
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