MC74HC4538A
http://onsemi.com
9
PIN DESCRIPTIONS
INPUTS
A1, A2 (Pins 4, 12)
Positive−edge trigger inputs. A rising−edge signal on
either of these pins triggers the corresponding multivibrator
when there is a high level on the B1 or B2 input.
B1, B2 (Pins 5, 11)
Negative−edge trigger inputs. A falling−edge signal on
either of these pins triggers the corresponding multivibrator
when there is a low level on the A1 or A2 input.
Reset 1, Reset 2 (Pins 3, 13)
Reset inputs (active low). When a low level is applied to
one of these pins, the Q output of the corresponding
multivibrator is reset to a low level and the Q
output is set to
a high level.
C
X
1/R
X
1 and C
X
2/R
X
2 (Pins 2 and 14)
External timing components. These pins are tied to the
common points of the external timing resistors and
capacitors (see the Block Diagram). Polystyrene capacitors
are recommended for optimum pulse width control.
Electrolytic capacitors are not recommended due to high
leakages associated with these type capacitors.
GND (Pins 1 and 15)
External ground. The external timing capacitors discharge
to ground through these pins.
OUTPUTS
Q1, Q2 (Pins 6, 10)
Noninverted monostable outputs. These pins (normally
low) pulse high when the multivibrator is triggered at either
the A or the B input. The width of the pulse is determined by
the external timing components, R
X
and C
X
.
Q1, Q2 (Pins 7, 9)
Inverted monostable outputs. These pins (normally high)
pulse low when the multivibrator is triggered at either the A
or the B input. These outputs are the inverse of Q1 and Q2.
+
−
+
−
RxCx
V
CC
M1
2 kW
M3
M2
A
B
RESET
POWER
ON
RESET
RESET LATCH
TRIGGER CONTROL
RESET CIRCUIT
TRIGGER
CONTROL CIRCUIT
OUTPUT
LATCH
UPPER
REFERENCE
CIRCUIT
V
re
,
UPPER
LOWER
REFERENCE
CIRCUIT
V
re
,
LOWER
Q
Q
C
CB
Q
R
V
CC
Figure 10. Logic Detail (1/2 the Device)
