96D3-2G1600NN-TRL Datasheet 96D3-2G1600NN-TRL | P4-P6

TS5KNN30100-6S

240Pin DDR3 1600 VLP UDIMM

2GB Based on 256Mx8

Transcend Information Inc.

Block Diagram

2GB, 256Mx64 Module(1 Rank x8)

/DQS1

DQS1

DM1

DQ 8

DQ 9

DQ 0

DQ 1

DQ 2

DQ 3

DQ 4

DQ 5

DQ 6

DQ 7

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

DQS/DQS

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

DQS/DQS

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

DQS/DQS

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

DQS/DQS

/DQS0

DQS0

DM0

/DQS2

DQS2

DM2

/DQS3

DQS3

DM3

/DQS5

DQS5

DM5

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

DQS/DQS

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

DQS/DQS

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

DQS/DQS

/DQS4

DQS4

DM4

/DQS6

DQS6

DM6

/DQS7

DQS7

DM7

I/O 0

I/O 1

I/O 2

I/O 3

I/O 4

I/O 5

I/O 6

I/O 7

DQS/DQS

BA0~BA2

A0~A15

CKE0

/RAS

/CAS

/WE

ODT0

CK0

/CK0

BA0–BA2: SDRAMs D0–D7

A0-A15: SDRAMs D0–D7

CKE: SDRAMs D0–D7

/RAS: SDRAMs D0–D7

/CAS: SDRAMs D0–D7

/WE: SDRAMs D0–D7

ODT: SDRAMs D0–D7

CK: SDRAMs D0–D7

/CK: SDRAMs D0–D7

VDDSP

VDD/VDDQ

VREFD

EEPRO

VREFC

D0~D7

NOTE:

DQ-to-I/O wiring is shown as recommended but may be

changed.

DQ,DQS,/DQS,ODT,DM,CKE,/S relationships must be

maintained as shown.

DQ,DM,DQS,/DQS resistors: Refer to associated topology

diagram

EEPRO

A1A0 A2

SA0SA1

SA2

/S0

This technical information is based on industry standard data and tests believed to be reliable. However, Transcend makes no warranties, either

expressed or implied, as to its accuracy and assume no liability in connection with the use of this product. Transcend reserves the right to make changes

in specifications at any time without prior notice

TS5KNN30100-6S

240Pin DDR3 1600 VLP UDIMM

2GB Based on 256Mx8

Transcend Information Inc.

Operating Temperature Condition

Parameter Symbol

Rating

Unit

Note

Operating Temperature TOPER

0 to 85 °C

1,2

Note:

1. Operating Temperature is the case surface temperature on the center/top side of the DRAM. For the

measurement conditions, please refer to JESD51-2 standard.

2. At 0 - 85°C, operation temperature range are the temperature which all DRAM specification will be

supported.

Absolute Maximum DC Ratings

Parameter Symbol Value Unit Note

Voltage on V

relative to Vss VDD -0.4 ~ 1.975 V 1

Voltage on V

DDQ

pin relative to Vss VDDQ -0.4 ~ 1.975 V 1

Voltage on any pin relative to Vss VIN, VOUT -0.4 ~ 1.975 V 1

Storage temperature T

STG

-55~+100 °C 1,2

Note:

1. Stress

greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the

device. This is a stress rating only and functional operation of the device at these or any other conditions

above those indicated in the operational sections of this specification is not implied. Exposure to absolute

maximum rating conditions for extended periods may affect reliability.

2. Storage Temperature is the case surface temperature on the center/top side of the DRAM. For the

measurement conditions, please refer to JESD51-2 standard.

AC & DC Operating Conditions

Recommended DC operating conditions (SSTL –1.5)

Parameter Symbol

Rating

Unit

Note

Min Typ. Max

Supply voltage VDD 1.425 1.5 1.575 V

1, 2

Supply voltage for Output VDDQ 1.425 1.5 1.575 V

1, 2

I/O Reference Voltage (DQ) VREF

(DC)

0.49*VDDQ

0.50*VDDQ

0.51*VDDQ V

I/O Reference Voltage (CMD/ADD) VREF

(DC)

0.49*VDDQ

0.50*VDDQ

0.51*VDDQ V

AC Input Logic High VIH

(AC)

VREF+0.175

- - V

AC Input Logic Low VIL

(AC)

- - VREF-0.175

DC Input Logic High VIH

(DC)

REF

+0.1 - VDD V

DC Input Logic Low VIL

(DC)

VSS - V

REF

-0.1 V

Note:

There is no specific device VDD supply voltage requirement for SSTL-1.5 compliance.

1. Under all conditions VDDQ must be less than or equal to VDD.

2. VDDQ tracks with VDD, AC parameters are measured with VDD and VDDQ tied together.

3. Peak to peak AC noise on VREF may not allow deviate from VREF(DC) by more than +/-1% VDD.

AC Input Level for Differential Signals

Parameter Symbol Value Unit Note

Differential Input Logical High V

IHdiff

+200 -

Differential Input Logical Low V

ILdiff

- -200

TS5KNN30100-6S

240Pin DDR3 1600 VLP UDIMM

2GB Based on 256Mx8

Transcend Information Inc.

IDD Specification parameters Definition

( IDD values are for full operating range of Voltage and Temperature)

2GB, 256Mx64 Module(1 Rank x8)

Parameter Symbol

DDR3

1600

CL11

Unit

Operating One bank Active

Precharge current;

tCK = tCK(IDD), tRC = tRC(IDD),

tRAS = tRASmin(IDD); CKE is HIGH, /CS is HIGH between valid com

mands;Address bus

inputs are SWITCHING; Data bus inputs are SWITCHING

IDD0

560 mA

Operating One bank Active

read

Precharge current;

IOUT = 0mA; BL = 8, CL =

CL(IDD), AL = 0; tCK = tCK(IDD), tRC = tRC (IDD), tRAS = tRASmin(IDD), tRCD =

tRCD(IDD); CKE is HIGH, /

CS is HIGH between valid commands; Address bus inputs are

SWITCHING; Data pattern is same as IDD4W

IDD1

640

Precharge power

down

current

;

All banks idle; tCK = tCK(IDD); CKE is LOW; Other

control and address bus inputs are STABLE; Data bus inputs are FLOATING

IDD2P

296

Precharge quiet standby current;

All banks idle; tCK = tCK(IDD); CKE is HIGH,

/CS is HIGH; Other control and address bus inputs are STABLE; Data bus inputs are

FLOATING

IDD2Q

320

Precharge standby current;

All banks idle; tCK = tCK(IDD); CKE is HIGH, /CS is

HIGH; Other control and address bus inputs are SWITCHING; Data bus inputs are

SWITCHING

IDD2N

344

Active power

down current;

All banks open; tCK = tCK(IDD); CKE is LOW; Other

control and address bus inputs are STABLE; Data bus inputs are FLOATING

IDD3P

400

Active standby current;

All banks open; tCK = tCK(IDD), tRAS = tRASmax(IDD), tRP

= tRP(IDD); CKE is HIGH, /CS is HIGH between valid commands; Other control and

address bus inputs are SWITCHING; Data bus inputs ar

e SWITCHING

IDD3N

440

Operating burst read current;

All banks open, Continuous burst reads, IOUT = 0mA;

BL = 4, CL = CL(IDD), AL = 0; tCK = tCK(IDD), tRAS = tRASmax(IDD), tRP = tRP(IDD);

CKE is HIGH, /CS is HIGH between valid commands; Address bus inputs are

SWITCHING; Data pattern is same as IDD4W

IDD4R

1248

Operating burst write current;

All banks open, Continuous burst writes; BL = 8, CL

= CL(IDD), AL = 0; tCK = tCK(IDD), tRAS = tRASmax(IDD), tRP = tRP(IDD); CKE is

HIGH, /CS is HIGH between valid commands; Address bus inputs are SWITCHING; Data

bus inputs are SWITCHING IDD4R

IDD4W

1160

Burst refresh current;

tCK = tCK(IDD); Refresh command at every tRFC(IDD)

interval; CKE is HIGH, /CS is HIGH between valid commands; Other control and address

bus inputs are SWITCHING; Data bus inputs are SWITCHING

IDD5

1560

Self refresh current;

CK and /CK at 0V; CKE ≒ 0.2V; Other control and address bus

inputs are FLOATING; Data bus inputs are FLOATING

IDD6

Operating bank interleave read current;

All bank interleaving reads, IOUT = 0mA;

BL = 8, CL = CL(IDD), AL = tRCD(IDD)-1*tCK(IDD); tCK = tCK(IDD), Trc = tRC(IDD),

tRRD = tRRD(IDD), tRCD = 1*tCK(IDD); CKE is HIGH, CS is HIGH between valid

commands;Address bus inputs are STABLE during DESELECTs; Data pattern is same

as IDD4R;

IDD7

1920

Note:

P1-P3 P4-P6 P7-P9 P10-P10

96D3-2G1600NN-TRL

Mfr. #:

Buy 96D3-2G1600NN-TRL

Manufacturer:

Advantech

Description:

Memory Modules 2G DDR3-1600 240PIN 256X8 VLP SAM(G)

Lifecycle:

New from this manufacturer.

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96D3-2G1600NN-TRL