TS5KNN30100-6S
240Pin DDR3 1600 VLP UDIMM
2GB Based on 256Mx8
Transcend Information Inc.
7
Timing Parameters & Specifications
Speed DDR3 1600 Unit
Parameter Symbol Min Max
Average Clock Period
tCK 1.25 <1.5 ns
CK high-level width
tCH 0.47 0.53 tCK
CK low-level width tCL 0.47 0.53 tCK
DQS, /DQS to DQ skew, per group, per access
tDQSQ - 100 ps
DQ output hold time from DQS, /DQS
tQH 0.38 - tCK
DQ low-impedance time from CK, /CK
tLZ(DQ) -450 225
ps
DQ high-impedance time from CK, /CK
tHZ(DQ) - 225
ps
Data setup time to DQS, /DQS reference to
Vih(ac)Vil(ac) levels
tDS 10 - ps
Data hold time to DQS, /DQS reference to
Vih(ac)Vil(ac) levels
tDH 45
ps
DQ and DM input pulse width for each input
tDIPW 360 - ps
DQS, /DQS Read preamble
tRPRE 0.9 - tCK
DQS, /DQS differential Read postamble
tRPST 0.3 - tCK
DQS, /DQS Write preamble
tWPRE 0.9 - tCK
DQS, /DQS Write postamble
tWPST 0.3 - tCK
DQS, /DQS low-impedance time
tLZ(DQS)
-450 225 ps
DQS, /DQS high-impedance time
tHZ(DQS)
- 225 ps
DQS, /DQS differential input low pulse width
tDQSL 0.45 0.55 tCK
DQS, /DQS differential input high pulse width
tDQSH 0.45 0.55 tCK
DQS, /DQS rising edge to CK, /CK rising edge
tDQSS -0.27 +0.27 tCK
DQS, /DQS falling edge setup time to CK, /CK
rising edge
tDSS
0.18 -
tCK
DQS, /DQS falling edge hold time to CK, /CK
rising edge
tDSH 0.18 - tCK
Delay from start of Internal write transaction to
Internal read command
tWTR
Max
(4tck, 7.5ns)
-
Write recovery time tWR
15 -
ns
Mode register set command cycle time
tMRD 4 - tCK
/CAS to /CAS command delay
tCCD
4 - nCK
Auto precharge write recovery + precharge time
tDAL
Active to active command period for 1KB page
size
tRRD
Max
(4tck, 6ns)
-
Active to active command period for 2KB page
size
tRRD
Max
(4tck, 7.5ns)
-
Four Activate Window for 1KB page size
products
tFAW 30 - ns
