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ACPL-34JT-000E

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P16
10
Switching Specications
Unless otherwise specied, all Minimum/Maximum specications are at recommended operating conditions, all volt-
ages at input IC are referenced to V
EE1
, all voltages at output IC referenced to V
EE2
. All typical values at T
A
= 25 °C, V
CC1
=
12 V, V
CC2
-V
EE2
= 20 V, V
E
-V
EE2
= 0 V.
Parameter Symbol Min Typ Max Units Test Conditions Fig Note
VIN to High Level Output
Propagation Delay Time
t
PLH
50 130 250 ns Rg = 10 Ω
Cg = 10 nF
f = 10 kHz
Duty Cycle = 50%
19-21 12
VIN to Low Level Output
Propagation Delay Time
t
PHL
50 150 280 ns 19-21 13
Pulse Width Distortion PWD 20 100 ns 14, 15
Propagation Delay Dierence
Between Any 2 Parts (t
PHL
-t
PLH
)
PDD 20 150 ns 15, 16
10% to 90% Rise Time t
R
60 ns
90% to 10% Fall Time t
F
50 ns
Desat Blanking Time t
DESAT(BLANKING)
0.6 1.0 µs Rg=10 Ohm,
Cg= 0 - 1nF
17
Desat Sense to 90% VOUT Delay t
DESAT(90%)
1.0 µs 18
Desat Sense to 10% VOUT Delay t
DESAT(10%)
2.0 µs 19
Desat to Desat Low Propagation Delay t
DESAT(LOW)
0.3 µs 20
Desat to Low Level FAULT Signal Delay t
DESAT(FAULT)
5 µs 21
Output Mute Time due to Desat t
DESAT(MUTE)
2.3 3.2 ms 22
Time Input Kept Low
Before Fault Reset to High
t
DESAT(RESET)
2.3 3.2 ms 23
VCC2 to UVLO High Delay t
PLH_UVLO
10 µs 24
VCC2 to UVLO Low Delay t
PHL_UVLO
10 µs 25
VCC2 UVLO to VOUT High Delay t
UVLO_ON
10 µs 26
VCC2 UVLO to VOUT Low Delay t
UVLO_OFF
10 µs 27
Output High Level Common Mode
Transient Immunity
|CM
H
| 30 >50 kV/μs T
A
=25°C, I
F
=10mA,
V
CM
=1500V,
V
CC1
=12V
22, 24,
26
28
Output Low Level Common Mode
Transient Immunity
|CM
L
| 30 >50 kV/μs T
A
= 25°C, I
F
=0mA,
V
CM
=1500V,
V
CC1
=12V
23, 25,
27
29
Package Characteristics
Parameter Symbol Min. Typ. Max. Units Test Conditions Note
Input-Output Momentary
Withstand Voltage
V
ISO
5000 VRMS RH < 50%, t = 1
min. TA = 25°C
30, 31, 32
Resistance (Input-Output) R
I-O
1014 Ω V
I-O
= 500 Vdc 32
Capacitance (Input-Output) C
I-O
1.3 pF f = 1 MHz
Thermal coecient between
LED and input IC
LED and output IC
input IC and output IC
LED and Ambient
input IC and Ambient
output IC and Ambient
A
EI
A
EO
A
IO
A
EA
A
IA
A
OA
35.4
33.1
25.6
176.1
92
76.7
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
11
Notes on Thermal Calculation
Application and environmental design for ACPL-34JT needs to ensure that the junction temperature of the internal ICs
and LED within the gate driver optocoupler do not exceed 150°C. The equations provided below are for the purposes of
calculating the maximum power dissipation and corresponding eect on junction temperatures.
LED Junction Temperature = A
EA
*P
E
+ A
EI
*P
I
+ A
EO
*P
O
+ T
A
Input IC Junction Temperature = A
EI
*P
E
+ A
IA
*P
I
+ A
IO
*P
O
+ T
A
Output IC Junction Temperature = A
EO
*P
E
+ A
IO
*P
I
+ A
OA
*P
O
+ T
A
P
E
- LED Power Dissipation
P
I
- Input IC Power Dissipation
P
O
- Output IC Power Dissipation
Calculation of LED Power Dissipation
LED Power Dissipation, P
E
= I
F(LED)
(Recommended Max) * V
F(LED)
(125°C) * Duty Cycle
Example: P
E
= 16mA * 1.25 * 50% duty cycle = 10mW
Calculation of Input IC Power Dissipation
Input IC Power Dissipation, P
I
= I
CC1
(Max) * V
CC1
(Recommended Max)
Example: P
I
= 6mA * 18V = 108mW
Calculation of Output IC Power Dissipation
Output IC Power Dissipation, P
O
= V
CC2
(Recommended Max) * I
CC2
(Max) + P
HS
+ P
LS
P
HS
- High Side Switching Power Dissipation
P
LS
- Low Side Switching Power Dissipation
P
HS
= (V
CC2
* Q
G
* f
PWM
) * R
OH(MAX)
/ (R
OH(MAX)
+ R
GH
) / 2
P
LS
= (V
CC2
* Q
G
* f
PWM
) * R
OL(MAX)
/ (R
OL(MAX)
+ R
GL
) / 2
Q
G
– IGBT Gate Charge at Supply Voltage
f
PWM
- LED Switching Frequency
R
OH(MAX)
– Maximum High Side Output Impedance - V
OH(MIN)
/ I
OH(MIN)
R
GH
- Gate Charging Resistance
R
OL(MAX)
– Maximum Low Side Output Impedance - V
OL(MIN)
/ I
OL(MIN)
R
GL
- Gate Discharging Resistance
Example:
R
OH(MAX)
= V
OH(MIN)
/ I
OH(MIN)
= 2.5V / 0.75A = 3.33Ω
R
OL(MAX)
= V
OL(MIN)
/ I
OL(MIN)
= 2.5V / 1A = 2.5Ω
P
HS
=(20V * 1uC * 10kHz) * 3.33Ω / (3.33Ω + 10Ω) / 2 = 24.98mW
P
LS
=(20V * 1uC * 10kHz) * 2.5Ω / (2.5Ω + 10Ω) / 2 = 20mW
PO
= 20V * 13.6mA + 24.98mW + 20mW = 316.98mW
Calculation of Junction Temperature
LED Junction Temperature = 176.1°C/W *10mW + 35.4°C/W *108mW + 33.1*316.98mW + T
A
= 16.1°C + T
A
Input IC Junction Temperature = 35.4°C/W *10mW + 92°C/W *108mW + 25.6*316.98mW + T
A
= 18.4°C + T
A
Output IC Junction Temperature = 33.1°C/W *10mW + 25.6°C/W *108mW + 76.7*316.98mW + T
A
= 27.4°C + T
A
12
Notes:
1. Output IC power dissipation is derated linearly above 100°C from 580mW to 260mW at 125°C.
2. Maximum pulse width = 1 μs, maximum duty cycle = 1%.
3. This supply is optional. Required only when negative gate drive is implemented.
4. Maximum 500ns pulse width if peak V
DESAT
> 10V
5. In most applications V
CC1
will be powered up rst (before V
CC2
) and powered down last (after V
CC2
). This is desirable for maintaining control of the
IGBT gate. In applications where V
CC2
is powered up rst, it is important to ensure that input remains low until V
CC1
reaches the proper operating
voltage to avoid any momentary instability at the output during V
CC1
ramp-up or ramp-down.
6. 15 V is the recommended minimum operating positive supply voltage (V
CC2
- V
E
) to ensure adequate margin in excess of the maximum V
UVLO+
threshold of 13.5 V.
7. For High Level Output Voltage testing, V
OH
is measured with a dc load current. When driving capacitive loads, V
OH
will approach V
CC
as I
OH
approaches zero.
8. Maximum pulse width = 1.0 ms, maximum duty cycle = 20%.
9. Once V
OUT
of the ACPL-34JT is allowed to go high (V
CC2
- V
E
> V
UVLO
), the DESAT detection feature of the ACPL-34JT will be the primary source of
IGBT protection. UVLO is needed to ensure DESAT is functional. Once V
CC2
exceeds VUVLO+ threshold, DESAT will remain functional until V
CC2
is
below V
UVLO-
threshold. Thus, the DESAT detection and UVLO features of the ACPL-34JT work in conjunction to ensure constant IGBT protection.
10. This is the “increasing” (i.e. turn-on or “positive going” direction) of V
CC2
- V
E
.
11. This is the “decreasing” (i.e. turn-o or “negative going” direction) of V
CC2
- V
E
.
12. t
PLH
is dened as propagation delay from 50% of LED input I
F
to 50% of High level output.
13. t
PHL
is dened as propagation delay from 50% of LED input I
F
to 50% of Low level output.
14. Pulse Width Distortion (PWD) is dened as |t
PHL
– t
PLH
| of any given unit.
15. As measured from I
F
to V
O
.
16. The dierence between t
PHL
and t
PLH
between any two ACPL-34JT parts under the same test conditions.
17. The delay time for ACPL-34JT to respond to a DESAT fault condition without any external DESAT capacitor.
18. The amount of time from when DESAT threshold is exceeded to 90% of V
GATE
at mentioned test conditions.
19. The amount of time from when DESAT threshold is exceeded to 10% of V
GATE
at mentioned test conditions.
20. The amount of time from when DESAT threshold is exceeded to DESAT Low voltage, 0.7 V.
21. The amount of time from when DESAT threshold is exceeded to FAULT output Low – 50% of VCC1 voltage.
22. The amount of time when DESAT threshold is exceeded, Output is mute to LED input.
23. The amount of time when DESAT Mute time is expired, LED input must be kept Low for Fault status to return to High.
24. The delay time when V
CC2
exceeds UVLO+ threshold to UVLO High – 50% of UVLO positive going edge.
25. The delay time when V
CC2
falls below UVLO- threshold to UVLO Low – 50% of UVLO negative going edge.
26. The delay time when V
CC2
exceeds UVLO+ threshold to 50% of High level output.
27. The delay time when V
CC2
falls below UVLO- threshold to 50% of Low level output.
28. Common mode transient immunity in the high state is the maximum tolerable dV
CM
/dt of the common mode pulse, V
CM
, to assure that the output
will remain in the high state (i.e., V
O
> 15 V or FAULT > 2 V or UVLO > 2V). A 330 pF and a 10 kΩ pull-up resistor is needed in fault and UVLO detection
mode.
29. Common mode transient immunity in the low state is the maximum tolerable dVCM/dt of the common mode pulse, V
CM
, to assure that the output
will remain in a low state (i.e., V
O
< 1.0 V or FAULT < 0.8 V or UVLO < 0.8 V). A 330 pF and a 10 kΩ pull-up resistor is needed in fault and UVLO
detection mode.
30. In accordance with UL1577, each optocoupler is proof tested by applying an insulation test voltage ≥6000 V
RMS
for 1 second.
31. The Input-Output Momentary Withstand Voltage is a dielectric voltage rating that should not be interpreted as an input-output continuous voltage
rating. For the continuous voltage rating refer to your equipment level safety specication or IEC/EN/DIN EN 60747-5-5 Insulation Characteristics
Table
32. Device considered a two terminal device: pins 1 - 8 shorted together and pins 9 - 16 shorted together.
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P16

ACPL-34JT-000E

Mfr. #:
Buy ACPL-34JT-000E
Manufacturer:
Broadcom / Avago
Description:
High Speed Optocouplers Optocouplers
Lifecycle:
New from this manufacturer.
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