MT88L70 Data Sheet
4
Zarlink Semiconductor Inc.
the steering time constants externally, allows the designer to tailor performance to meet a wide variety of system
requirements.
Table 1 - Functional Decode Table
L=LOGIC LOW, H=LOGIC HIGH, Z=HIGH IMPEDANCE
X = DON‘T CARE
Guard Time Adjustment
In many situations not requiring selection of tone duration and interdigital pause, the simple steering circuit shown
in Figure 3 is applicable. Component values are chosen according to the formula:
t
REC
=t
DP
+t
GTP
t
ID
=t
DA
+t
GTA
The value of t
DP
is a device parameter (see Figure 7) and t
REC
is the minimum signal duration to be recognized by
the receiver. A value for C of 0.1 µF is recommended for most applications, leaving R to be selected by the
designer.
Digit TOE INH ESt Q
4
Q
3
Q
2
Q
1
ANYLXHZZZZ
1 HXH0001
2 HXH0010
3 HXH0011
4 HXH0100
5 HXH0101
6 HXH0110
7 HXH0111
8 HXH1000
9 HXH1001
0 HXH1010
* HXH1011
# HXH1100
A HLH1101
B HLH1110
C HLH1111
D HLH0000
AHHL
undetected, the output code
will remain the same as the
previous detected code
BHHL
CHHL
DHHL
MT88L70 Data Sheet
5
Zarlink Semiconductor Inc.
Figure 3 - Basic Steering Circuit
Different steering arrangements may be used to select independently the guard times for tone present (t
GTP
) and
tone absent (t
GTA
). This may be necessary to meet system specifications which place both accept and reject limits
on both tone duration and interdigital pause. Guard time adjustment also allows the designer to tailor system
parameters such as talk off and noise immunity. Increasing t
REC
improves talk-off performance since it reduces the
probability that tones simulated by speech will maintain signal condition long enough to be registered. Alternatively,
a relatively short t
REC
with a long t
DO
would be appropriate for extremely noisy environments where fast acquisition
time and immunity to tone drop-outs are required. Design information for guard time adjustment is shown in Figure
4.
Power-down and Inhibit Mode
A logic high applied to pin 6 (PWDN) will power down the device to minimize the power consumption in a standby
mode. It stops the oscillator and the functions of the filters.
Inhibit mode is enabled by a logic high input to the pin 5 (INH). It inhibits the detection of tones representing
characters A, B, C, and D. The output code will remain the same as the previous detected code (see Table 1).
Figure 4 - Guard Time Adjustment
C
v
c
V
DD
St/GT
ESt
StD
MT88L70
R
t
GTA
=(RC)In(V
DD
/V
TSt
)
t
GTP
=(RC)In[V
DD
/(V
DD
-V
TSt
)]
V
DD
V
DD
St/GT
ESt
R
1
C
1
R
2
V
DD
St/GT
ESt
C
1
R
1
R
2
a) decreasing t
GTP
; (t
GTP
< t
GTA
)
b) decreasing t
GTA
; (t
GTP
> t
GTA
)
t
GTA
=(R
1
C
1
) In (V
DD
/ V
TSt
)
t
GTP
=(R
P
C
1
) In [V
DD
/ (V
DD
-V
TSt
)]
R
P
= (R
1
R
2
) / (R
1
+ R
2
)
t
GTA
=(R
P
C
1
) In (V
DD
/ V
TSt
)
t
GTP
=(R
1
C
1
) In [V
DD
/ (V
DD
-V
TSt
)]
R
P
= (R
1
R
2
) / (R
1
+ R
2
)
MT88L70 Data Sheet
6
Zarlink Semiconductor Inc.
Differential Input Configuration
The input arrangement of the MT88L70 provides a differential-input operational amplifier as well as a bias source
(V
Ref
) which is used to bias the inputs at mid-rail. Provision is made for connection of a feedback resistor to the op-
amp output (GS) for adjustment of gain. In a single-ended configuration, the input pins are connected as shown in
Figure 6 with the op-amp connected for unity gain and V
Ref
biasing the input at 1/2V
DD
. Figure 5 shows the
differential configuration, which permits the adjustment of gain with the feedback resistor R
5
.
Figure 5 - Differential Input Configuration
Crystal Oscillator
The internal clock circuit is completed with the addition of an external 3.579545 MHz crystal and is connected as
shown in Figure 6 (Single-ended Input Configuration).
C
1
R
1
C
2
R
4
IN+
IN-
R
5
R
2
R
3
GS
V
Ref
+
-
MT88L70
DIFFERNTIAL INPUT AMPLIFIER
C
1
= C
2
= 10 nF
R
1
= R
4
= R
5
= 100 k
R
2
= 60 k, R
3
, = 37.5 k
R
3
=
R
2
R
5
R
2
+ R
5
VOLTAGE GAIN (A
V
diff) =
R5
R1
INPUT IMPEDANCE
(Z
INDIFF
) = 2
R
1
2
+
1
ωC
2
All resistors are ± 1% tolerance.
All capacitors are ± 5% tolerance.

MT88L70AN1

Mfr. #:
Manufacturer:
Microchip / Microsemi
Description:
Telecom Interface ICs Pb Free 3 VOLT INTEGRATED DTMF RECEIVER
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
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