16
COMMERCIAL TEMPERATURE RANGE
IDT72V3686/72V3696/72V36106 3.3V CMOS TRIPLE BUS SyncFIFO
TM
WITH BUS-MATCHING 16,384 x 36 x 2, 32,768 x 36 x 2, 65, 536 x 36
[16,384/32,768/65,536-(Y+1)]. An Almost-Full flag is set HIGH by the second
LOW-to-HIGH transition of its synchronizing clock after the FIFO read that
reduces the number of words in memory to [16,384/32,768/65,536-(Y+1)]. A
LOW-to-HIGH transition of an Almost-Full flag synchronizing clock begins the
first synchronization cycle if it occurs at time tSKEW2 or greater after the read that
reduces the number of words in memory to [16,384/32,768/65,536-(Y+1)].
Otherwise, the subsequent synchronizing clock cycle may be the first synchro-
nization cycle (see Figure 26 and 27).
MAILBOX REGISTERS
Each FIFO has an 18-bit bypass register allowing the passage of command
and control information from Port A to Port B or from Port C to Port A without putting
it in queue. The Mailbox Select (MBA, MBB and MBC) inputs choose between
a mail register and a FIFO for a port data transfer operation. The usable width
of both the Mail1 and Mail2 registers matches the selected bus size for ports B
and C.
When sending data from Port A to Port B via the Mail1 Register, the following
is the case: A LOW-to-HIGH transition on CLKA writes data to the Mail1 Register
when a Port A write is selected by CSA, W/RA, and ENA with MBA HIGH. If
the selected Port B bus size is 18 bits, then the usable width of the Mail1 Register
employs data lines A0-A17. (In this case, A18-A35 are don’t care inputs.) If
the selected Port B bus size is 9 bits, then the usable width of the Mail1 Register
employs data lines A0-A8. (In this case, A9-A35 are don’t care inputs.)
When sending data from Port C to Port A via the Mail2 Register, the following
is the case: A LOW-to-HIGH transition on CLKC writes data to the Mail2 Register
when a Port C write is selected by WENC with MBC HIGH. If the selected Port
C bus size is 18 bits, then the usable width of the Mail2 Register employs data
lines C0-C17. If the selected Port C bus size is 9 bits, then the usable width of
the Mail2 Register employs data lines C0-C8. (In this case, C9-C17 are don’t
care inputs.)
Writing data to a mail register sets its corresponding flag (MBF1 or MBF2)
LOW. Attempted writes to a mail register are ignored while the mail flag is LOW.
When data outputs of a port are active, the data on the bus comes from the
FIFO output register when the port Mailbox select input is LOW and from the
mail register when the port mailbox select input is HIGH.
The Mail1 Register Flag (MBF1) is set HIGH by a LOW-to-HIGH transition
on CLKB when a Port B read is selected by CSB, and RENB with MBB HIGH.
For an 18-bit bus size, 18 bits of mailbox data are placed on B0-B17. For the
9-bit bus size, 9 bits of mailbox data are placed on B0-B8. (In this case, B9-B17
are indeterminate.)
The Mail2 Register Flag (MBF2) is set HIGH by a LOW-to-HIGH transition
on CLKA when a Port A read is selected by CSA, W/RA, and ENA with MBA
HIGH. The data in a mail register remains intact after it is read and changes only
when new data is written to the register. For an 18-bit bus size, 18 bits of mailbox
data appear on A18-A35. (In this case, A0-A17 are indeterminate.) For a 9-
bit bus size, 9 bits of mailbox data appear on A18-A26. (In this case, A0-A17
and A27-A35 are indeterminate.)
The data in a mail register remains intact after it is read and changes only
when new data is written to the register. The Endian Select feature has no effect
on mailbox data.
Note that MBC must be HIGH during Master Reset (until FFA/IRA and FFC/
IRC go HIGH. MBA and MBB are don't care inputs during Master Reset. For
mail register and mail register flag timing diagrams, see Figure 28 and 29.
BUS SIZING
Port B may be configured in either an 18-bit word or a 9-bit byte format for
data read from FIFO1. Port C may be configured in either an 18-bit word or
a 9-bit byte format for data written to FIFO2. The bus size can be selected
independently for Ports B and C. The level applied to the Port B Size Select
(SIZEB) input determines the Port B bus size and the level applied to the Port
C Size Select (SIZEC) input determines the Port C bus size. These levels should
be static throughout FIFO operation. Both bus size selections are implemented
at the completion of Master Reset, by the time the Full/Input Ready flag is set
HIGH, as shown in Figure 2 and 3.
Two different methods for sequencing data transfer are available for Ports
B and C regardless of whether the bus size selection is byte- or word-size. They
are referred to as Big-Endian (most significant byte first) and Little-Endian (least
significant byte first). The level applied to the Big-Endian Select (BE) input during
the LOW-to-HIGH transition of MRS1 and MRS2 selects the endian method that
will be active during FIFO operation. This selection applies to both ports B and
C. The endian method is implemented at the completion of Master Reset, by
the time the Full/Input Ready flag is set HIGH, as shown in Figure 2 and 3 (see
Endian Selection section).
Only 36-bit long word data is written to or read from the two FIFO memories
on these devices. Bus-Matching operations are done after data is read from
the FIFO1 RAM (Port B) and before data is written to the FIFO2 RAM (Port
C). The Endian select operations are not available when transferring data via
mailbox registers. Furthermore, both the word- and byte-size bus selections
limit the width of the data bus that can be used for mail register operations. In
this case, only those byte lanes belonging to the selected word- or byte-size
bus can carry mailbox data. The remaining data outputs will be indeterminate.
The remaining data inputs will be don’t care inputs. For example, when a word-
size bus is selected on Port B, then mailbox data can be transmitted only from
A0-A17 to B0-B17. When a byte-size bus is selected on Port B, then mailbox
data can be transmitted only from A0-A8 to B0-B8. Similarly, when a word-size
bus is selected on Port C, then mailbox data can be transmitted only from C0-
C17 to A18-A35. When a byte-size bus is selected on Port C, then mailbox data
can be transmitted only from C0-C8 to A18-A26.
BUS-MATCHING FIFO1 READS
Data is read from the FIFO1 RAM in 36-bit long word increments. Since Port
B can have a byte or word size, only the first one or two bytes appear on the
selected portion of the FIFO1 output register, with the rest of the long word stored
in auxiliary registers. In this case, subsequent FIFO1 reads output the rest of
the long word to the FIFO1 output register in the order shown by Figure 2.
When reading data from FIFO1 in byte format, the unused B9-B17 outputs
are indeterminate.
BUS-MATCHING FIFO2 WRITES
Data is written to the FIFO2 RAM in 36-bit long word increments. Data written
to FIFO2 with a byte or word bus size stores the initial bytes or words in auxiliary
registers. The CLKC rising edge that writes the fourth byte or the second word
of long word to FIFO2 also stores the entire long word in the FIFO2 memory.
The bytes are arranged in the manner shown in Figure 3.
When writing data to FIFO2 in byte format, the unused C9-C17 inputs are
don't care inputs.
