9
COMMERCIAL TEMPERATURE RANGE
IDT72V3686/72V3696/72V36106 3.3V CMOS TRIPLE BUS SyncFIFO
TM
WITH BUS-MATCHING 16,384 x 36 x 2, 32,768 x 36 x 2, 65, 536 x 36
TIMING REQUIREMENTS OVER RECOMMENDED RANGES OF SUPPLY
VOLTAGE AND OPERATING FREE-AIR TEMPERATURE
IDT72V3686L10 IDT72V3686L15
IDT72V3696L10 IDT72V3696L15
IDT72V36106L10 IDT72V36106L15
Symbol Parameter Min. Max. Min. Max. Unit
fS Clock Frequency, CLKA, CLKB, or CLKC — 100 — 66.7 MHz
tCLK Clock Cycle Time, CLKA, CLKB, or CLKC 10 — 15 — ns
tCLKH Pulse Duration, CLKA, CLKB, or CLKC HIGH 4.5 — 6 — ns
tCLKL Pulse Duration, CLKA, CLKB, OR CLKC LOW 4.5 — 6 — ns
tDS Setup Time, A0-A35 before CLKA↑ and C0-C17 before CLKC↑ 3—4—ns
tENS1 Setup Time, CSA and W/RA before CLKA↑; CSB 4 — 4.5 — ns
before CLKB↑
tENS2 Setup Time, ENA, and MBA before CLKA↑; RENB 3 — 4.5 — ns
and MBB before CLKB↑; WENC and MBC before CLKC↑
tRSTS Setup Time, MRS1, MRS2, PRS1, PRS2, RT1 or RT2 5—5—ns
LOW before CLKA↑ or CLKB↑
(1)
tFSS Setup Time, FS0, FS1, FS2 before MRS1 and MRS2 HIGH 7.5 — 8.5 — ns
tBES Setup Time, BE/FWFT before MRS1 and MRS2 HIGH 7.5 — 7.5 — ns
tSDS Setup Time, FS0/SD before CLKA↑ 3—4—ns
tSENS Setup Time, FS1/SEN before CLKA↑ 3—4—ns
tFWS Setup Time, BE/FWFT before CLKA↑ 0—0—ns
tRTMS Setup Time, RTM before RT1; RTM before RT2 5—5—ns
tDH Hold Time, A0-A35 after CLKA↑ and C0-C17 after CLKC↑ 0.5 — 1 — ns
tENH Hold Time, CSA, W/RA, ENA, and MBA after CLKA↑; CSB, 0.5 — 1 — ns
RENB, and MBB after CLKB↑; WENC and MBC after CLKC↑
tRSTH Hold Time, MRS1, MRS2, PRS1, PRS2, RT1 or RT2 4—4—ns
LOW after CLKA↑ or CLKB↑
(1)
tFSH Hold Time, FS0, FS1, FS2 after MRS1 and MRS2 HIGH 2 — 2 — ns
tBEH Hold Time, BE/FWFT after MRS1 and MRS2 HIGH 2 — 2 — ns
tSDH Hold Time, FS0/SD after CLKA↑ 0.5 — 1 — ns
tSENH Hold Time, FS1/SEN HIGH after CLKA↑ 0.5 — 1 — ns
tSPH Hold Time, FS1/SEN HIGH after MRS1 and MRS2 HIGH 2 — 2 — ns
tRTMH Hold Time, RTM after RT1; RTM after RT2 5—5—ns
tSKEW1
(2)
Skew Time, between CLKA↑ and CLKB↑ for EFB/ORB and 5 — 7.5 — ns
FFA/IRA; between CLKA↑ and CLKC↑ for EFA/ORA and
FFC/IRC
tSKEW2
(2,3)
Skew Time, between CLKA↑ and CLKB↑ for AEB and AFA;12—12—ns
between CLKA↑ and CLKC↑ for AEA and AFC
NOTES:
1. Requirement to count the clock edge as one of at least four needed to reset a FIFO.
2. Skew time is not a timing constraint for proper device operation and is only included to illustrate the timing relationship among CLKA cycle, CLKB cycle, and CLKC cycle.
3. Design simulated, not tested.
(Vcc = 3.3V ± 0.15V; TA = 0
ο
C to +70
ο
C; JEDEC JESD8-A compliant)