OMO ElectronicOMO Electronic
Expand menu
Hello, Sign inMy Account
0 Cart

AD9814JR

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P16
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
a
AD9814
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700 World Wide Web Site: http://www.analog.com
Fax: 781/326-8703 © Analog Devices, Inc., 1999
Complete 14-Bit
CCD/CIS Signal Processor
FUNCTIONAL BLOCK DIAGRAM
9-BIT
DAC
PGACDS
PGA
9-BIT
DAC
CDS
9-BIT
DAC
PGACDS
3:1
MUX
14-BIT
ADC
14
14:8
MUX
8
BANDGAP
REFERENCE
CONFIGURATION
REGISTER
MUX
REGISTER
BLUE
GREEN
RED
BLUE
GREEN
RED
6
9
GAIN
REGISTERS
OFFSET
REGISTERS
DIGITAL
CONTROL
INTERFACE
INPUT
CLAMP
BIAS
AD9814
DRVDD DRVSSAVDD AVSSCAPT CAPBAVDD AVSS CML
OEB
DOUT
SCLK
SLOAD
SDATA
ADCCLKCDSCLK2CDSCLK1
OFFSET
VINB
VING
VINR
FEATURES
14-Bit 10 MSPS A/D Converter
No Missing Codes Guaranteed
3-Channel Operation Up to 10 MSPS
1-Channel Operation Up to 7 MSPS
Correlated Double Sampling
1-6x Programmable Gain
ⴞ300 mV Programmable Offset
Input Clamp Circuitry
Internal Voltage Reference
Multiplexed Byte-Wide Output (8+6 Format)
3-Wire Serial Digital Interface
+3/+5 V Digital I/O Compatibility
28-Lead SOIC Package
Low Power CMOS: 330 mW (Typ)
Power-Down Mode: <1 mW
APPLICATIONS
Flatbed Document Scanners
Film Scanners
Digital Color Copiers
Multifunction Peripherals
PRODUCT DESCRIPTION
The AD9814 is a complete analog signal processor for CCD
imaging applications. It features a 3-channel architecture de-
signed to sample and condition the outputs of trilinear color
CCD arrays. Each channel consists of an input clamp, Corre-
lated Double Sampler (CDS), offset DAC and Programmable
Gain Amplifier (PGA), multiplexed to a high performance 14-
bit A/D converter.
The CDS amplifiers may be disabled for use with sensors such
as Contact Image Sensors (CIS) and CMOS active pixel sen-
sors, which do not require CDS.
The 14-bit digital output is multiplexed into an 8-bit output
word that is accessed using two read cycles. The internal regis-
ters are programmed through a 3-wire serial interface, and pro-
vide adjustment of the gain, offset, and operating mode.
The AD9814 operates from a single +5 V power supply, typi-
cally consumes 330 mW of power, and is packaged in a 28-lead
SOIC.
AD9814* PRODUCT PAGE QUICK LINKS
Last Content Update: 02/23/2017
COMPARABLE PARTS
View a parametric search of comparable parts.
DOCUMENTATION
Application Notes
• AN-297: Test Video A/D Converters Under Dynamic
Conditions
Data Sheet
• AD9814: Complete 14-Bit CCD/CIS Signal Processor Data
Sheet
REFERENCE MATERIALS
Technical Articles
• Analog Exposes Front End for Digital Cameras
• High Integration Simplifies Signal Processing For CCDs
DESIGN RESOURCES
• AD9814 Material Declaration
• PCN-PDN Information
• Quality And Reliability
• Symbols and Footprints
DISCUSSIONS
View all AD9814 EngineerZone Discussions.
SAMPLE AND BUY
Visit the product page to see pricing options.
TECHNICAL SUPPORT
Submit a technical question or find your regional support
number.
DOCUMENT FEEDBACK
Submit feedback for this data sheet.
This page is dynamically generated by Analog Devices, Inc., and inserted into this data sheet. A dynamic change to the content on this page will not
trigger a change to either the revision number or the content of the product data sheet. This dynamic page may be frequently modified.
REV. 0
–2–
AD9814–SPECIFICATIONS
ANALOG SPECIFICATIONS
J-Grade K-Grade
Parameter Min Typ Max Min Typ Max Units
CONVERSION RATE
3-Channel Mode with CDS 6 10 6 10 MSPS
1-Channel Mode with CDS 6 7 6 7 MSPS
ACCURACY (Entire Signal Path)
ADC Resolution 14 14 Bits
Integral Nonlinearity
1
(INL) +2.5/–6.0 +2.5/–6.0 ±11.0 LSB
INL @ 10 MHz +4.0/–7.0 +4.0/–7.0 LSB
Differential Nonlinearity (DNL) +0.6/–0.5 +0.6/–0.5 ±1.0 LSB
DNL @ 10 MHz +0.8/–0.6 +0.8/–0.6 LSB
No Missing Codes Guaranteed 13 14 Bits
Offset Error –12 –12 ±104 mV
Gain Error
2
2.2 2.2 ±5.3 % FSR
ANALOG INPUTS
Input Signal Range
3
4.0 4.0 V p-p
Allowable Reset Transient
3
1.0 1.0 V
Input Limits
4
AVSS – 0.3 AVDD + 0.3 AVSS – 0.3 AVDD + 0.3 V
Input Capacitance 10 10 pF
Input Bias Current 10 10 nA
AMPLIFIERS
PGA Gain at Minimum 1 1 V/V
PGA Gain at Maximum 5.8 5.8 V/V
PGA Resolution 64 64 Steps
PGA Monotonicity Guaranteed Guaranteed
Programmable Offset at Minimum –300 –300 mV
Programmable Offset at Maximum +300 +300 mV
Programmable Offset Resolution 512 512 Steps
Programmable Offset Monotonicity Guaranteed Guaranteed
NOISE AND CROSSTALK
Input Referred Noise @ PGA Min 130 130 µV rms
Total Output Noise @ PGA Min 0.55 0.55 LSB rms
Input Referred Noise @ PGA Max 84 84 µV rms
Total Output Noise @ PGA Max 2.0 2.0 LSB rms
Channel-Channel Crosstalk <1 <1 LSB
POWER SUPPLY REJECTION
AVDD = +5 V ± 0.25 V 0.07 0.07 0.3 % FSR
Differential VREF (@ +25°C)
CAPT-CAPB (4 V Input Range) 2.0 1.9 2.0 2.1 V
CAPT-CAPB (2 V Input Range) 1.0 0.94 1.0 1.06 V
TEMPERATURE RANGE
Operating 0 +70 0 +70 °C
Storage –65 +150 –65 +150 °C
POWER SUPPLIES
AVDD +4.75 +5.0 +5.25 +4.75 +5.0 +5.25 V
DRVDD +3.0 +5.0 +5.25 +3.0 +5.0 +5.25 V
Total Operating Current
AVDD 64 64 80 mA
DRVDD 1.8 1.8 10 mA
Power-Down Mode Current 150 150 µA
Power Dissipation 330 330 450 mW
Power Dissipation @ 10 MHz 355 355 mW
Power Dissipation (1-Channel Mode) 220 220 265 mW
(T
MIN
to T
MAX
, AVDD = +5 V, DRVDD = +5 V, 3-Channel CDS Mode, f
ADCCLK
= 6 MHz, f
CDSCLK1
= f
CDSCLK2
=
2 MHz, PGA Gain = 1, Input Range = 4 V, unless otherwise noted.)
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P16

AD9814JR

Mfr. #:
Buy AD9814JR
Manufacturer:
Analog Devices Inc.
Description:
Analog Front End - AFE 14-Bit 3CH CCD Signal Processor
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union

Products related to this Datasheet