REV. 0 –3
AD9814
DIGITAL SPECIFICATIONS
Parameter Symbol Min Typ Max Units
LOGIC INPUTS
High Level Input Voltage V
IH
2.6 V
Low Level Input Voltage V
IL
0.8 V
High Level Input Current I
IH
10 µA
Low Level Input Current I
IL
10 µA
Input Capacitance C
IN
10 pF
LOGIC OUTPUTS
High Level Output Voltage V
OH
4.5 V
Low Level Output Voltage V
OL
0.1 V
High Level Output Current I
OH
50 µA
Low Level Output Current I
OL
50 µA
Specifications subject to change without notice.
TIMING SPECIFICATIONS
Parameter Symbol Min Typ Max Units
CLOCK PARAMETERS
3-Channel Pixel Rate t
PRA
300 500 ns
1-Channel Pixel Rate t
PRB
140 ns
ADCCLK Pulsewidth t
ADCLK
45 ns
CDSCLK1 Pulsewidth t
C1
20 ns
CDSCLK2 Pulsewidth t
C2
40 ns
CDSCLK1 Falling to CDSCLK2 Rising t
C1C2
0ns
ADCCLK Falling to CDSCLK2 Rising t
ADC2
10 ns
CDSCLK2 Rising to ADCCLK Rising t
C2ADR
10 ns
CDSCLK2 Falling to ADCCLK Falling t
C2ADF
50 ns
CDSCLK2 Falling to CDSCLK1 Rising t
C2C1
50 ns
ADCCLK Falling to CDSCLK1 Rising t
ADC1
0ns
Aperture Delay for CDS Clocks t
AD
3ns
SERIAL INTERFACE
Maximum SCLK Frequency f
SCLK
10 MHz
SLOAD to SCLK Set-Up Time t
LS
10 ns
SCLK to SLOAD Hold Time t
LH
10 ns
SDATA to SCLK Rising Set-Up Time t
DS
10 ns
SCLK Rising to SDATA Hold Time t
DH
10 ns
SCLK Falling to SDATA Valid t
RDV
10 ns
DATA OUTPUT
Output Delay t
OD
6ns
3-State to Data Valid t
DV
16 ns
Output Enable High to 3-State t
HZ
5ns
Latency (Pipeline Delay) 3 (Fixed) Cycles
Specifications subject to change without notice.
(T
MIN
to T
MAX
, AVDD = +5 V, DRVDD = +5 V, CDS Mode, f
ADCCLK
= 6 MHz, f
CDSCLK1
= f
CDSCLK2
= 2 MHz,
C
L
= 10 pF, unless otherwise noted.)
(T
MIN
to T
MAX
, AVDD = +5 V, DRVDD = +5 V)
NOTES
1
The Integral Nonlinearity in measured using the “fixed endpoint” method, NOT using a “best-fit” calculation. See Definitions of Specifications.
2
The Gain Error specification is dominated by the tolerance of the internal differential voltage reference.
3
Linear input signal range is from 0 V to 4 V when the CCD’s reference level is clamped to 4 V by the AD9814’s input clamp. A larger reset transient can be tolerated
by using the 3 V clamp level instead of the nominal 4 V clamp level. Linear input signal range will be from 0 V to 3 V when using the 3 V clamp level.
1V TYP
RESET TRANSIENT
4V SET BY INPUT CLAMP (3V OPTION ALSO AVAILABLE)
4V p-p MAX INPUT SIGNAL RANGE
GND
4
The input limits are defined as the maximum tolerable voltage levels into the AD9814. These levels are not intended to be in the linear input range of the device.
Signals beyond the input limits will turn on the overvoltage protection diodes.
5
The PGA Gain is approximately “linear in dB” and follows the equation:
Gain =
+
[
.
.[ ]
]
58
148
63 –G
63
where G is the register value. See Figure 13.
Specifications subject to change without notice.
REV. 0
AD9814
–4–
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD9814 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
ABSOLUTE MAXIMUM RATINGS*
With
Respect
Parameter To Min Max Units
VIN, CAPT, CAPB AVSS –0.3 AVDD + 0.3 V
Digital Inputs AVSS –0.3 AVDD + 0.3 V
AVDD AVSS –0.5 +6.5 V
DRVDD DRVSS –0.5 +6.5 V
AVSS DRVSS –0.3 +0.3 V
Digital Outputs DRVSS –0.3 DRVDD + 0.3 V
Junction Temperature +150
°
C
Storage Temperature –65 +150
°
C
Lead Temperature
(10 sec) +300
°C
*Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum ratings
for extended periods may affect device reliability.
ORDERING GUIDE
Temperature Package
Model Range Description
AD9814JR 0°C to +70°C 28-Lead 300 Mil SOIC
AD9814KR 0°C to +70°C 28-Lead 300 Mil SOIC
THERMAL CHARACTERISTICS
Thermal Resistance
28-Lead 300 Mil SOIC
θ
JA
= 71.4°C/W
θ
JC
= 23°C/W
PIN CONFIGURATION
TOP VIEW
(Not to Scale)
28
27
26
25
24
23
22
21
20
19
18
17
16
15
1
2
3
4
5
6
7
8
9
10
11
12
13
14
AD9814
CDSCLK1 AVDD
CDSCLK2 AVSS
ADCCLK VINR
OEB OFFSET
DRVDD VING
DRVSS CML
(MSB) D7 VINB
D6 CAPT
D5 CAPB
D4 AVSS
D3 AVDD
D2 SLOAD
D1 SCLK
(LSB) D0 SDATA
PIN FUNCTION DESCRIPTIONS
Pin
N
o. Name Type Description
1 CDSCLK1 DI CDS Reference Level Sampling
Clock
2 CDSCLK2 DI CDS Data Level Sampling Clock
3 ADCCLK DI A/D Converter Sampling Clock
4 OEB DI Output Enable, Active Low
5 DRVDD P Digital Output Driver Supply
6 DRVSS P Digital Output Driver Ground
7 D7 DO Data Output MSB. ADC DB13
High Byte, ADC DB5 Low Byte
8 D6 DO Data Output. ADC DB12 High
Byte, ADC DB4 Low Byte
9 D5 DO Data Output. ADC DB11 High
Byte, ADC DB3 Low Byte
10 D4 DO Data Output. ADC DB10 High
Byte, ADC DB2 Low Byte
11 D3 DO Data Output. ADC DB9 High
Byte, ADC DB1 Low Byte
12 D2 DO Data Output. ADC DB8 High
Byte, ADC DB0 Low Byte
13 D1 DO Data Output. ADC DB7 High
Byte, Don’t Care Low Byte
14 D0 DO Data Output LSB. ADC DB6
High Byte, Don’t Care Low Byte
15 SDATA DI/DO Serial Interface Data Input/Output
16 SCLK DI Serial Interface Clock Input
17 SLOAD DI Serial Interface Load Pulse
18 AVDD P +5 V Analog Supply
19 AVSS P Analog Ground
20 CAPB AO ADC Bottom Reference Voltage
Decoupling
21 CAPT AO ADC Top Reference Voltage
Decoupling
22 VINB AI Analog Input, Blue Channel
23 CML AO Internal Bias Level Decoupling
24 VING AI Analog Input, Green Channel
25 OFFSET AO Clamp Bias Level Decoupling
26 VINR AI Analog Input, Red Channel
27 AVSS P Analog Ground
28 AVDD P +5 V Analog Supply
TYPE: AI = Analog Input, AO = Analog Output, DI = Digital Input, DO =
Digital Output, P = Power.
REV. 0
AD9814
–5–
DEFINITIONS OF SPECIFICATIONS
INTEGRAL NONLINEARITY (INL)
Integral nonlinearity error refers to the deviation of each indi-
vidual code from a line drawn from “zero scale” through “posi-
tive full scale.” The point used as “zero scale” occurs 1/2 LSB
before the first code transition. “Positive full scale” is defined as
a level 1 1/2 LSB beyond the last code transition. The deviation
is measured from the middle of each particular code to the true
straight line.
DIFFERENTIAL NONLINEARITY (DNL)
An ideal ADC exhibits code transitions that are exactly 1 LSB
apart. DNL is the deviation from this ideal value. Thus every
code must have a finite width. No missing codes guaranteed to
14-bit resolution indicates that all 16384 codes, respectively,
must be present over all operating ranges.
OFFSET ERROR
The first ADC code transition should occur at a level 1/2 LSB
above the nominal zero scale voltage. The offset error is the
deviation of the actual first code transition level from the ideal
level.
GAIN ERROR
The last code transition should occur for an analog value
1 1/2 LSB below the nominal full-scale voltage. Gain error is
the deviation of the actual difference between first and last code
transitions and the ideal difference between the first and last
code transitions.
INPUT REFERRED NOISE
The rms output noise is measured using histogram techniques.
The ADC output codes’ standard deviation is calculated in
LSB, and converted to an equivalent voltage, using the relation-
ship 1 LSB = 4 V/16384 = 244 mV. The noise is then referred
to the input of the AD9814 by dividing by the PGA gain.
CHANNEL-TO-CHANNEL CROSSTALK
In an ideal three channel system, the signal in one channel will
not influence the signal level of another channel. The channel-
to-channel crosstalk specification is a measure of the change that
occurs in one channel as the other two channels are varied. In
the AD9814, one channel is grounded and the other two chan-
nels are exercised with full-scale input signals. The change in the
output codes from the first channel is measured and compared
with the result when all three channels are grounded. The differ-
ence is the channel-to-channel crosstalk, stated in LSB.
APERTURE DELAY
The aperture delay is the time delay that occurs from when a
sampling edge is applied to the AD9814 until the actual sample
of the input signal is held. Both CDSCLK1 and CDSCLK2
sample the input signal during the transition from high to low,
so the aperture delay is measured from each clock’s falling edge
to the instant the actual internal sample is taken.
POWER SUPPLY REJECTION
Power Supply Rejection specifies the maximum full-scale change
that occurs from the initial value when the supplies are varied
over the specified limits.

AD9814JR

Mfr. #:
Manufacturer:
Analog Devices Inc.
Description:
Analog Front End - AFE 14-Bit 3CH CCD Signal Processor
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
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