NCP1597A
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10
PROTECTIONS
Undervoltage Lockout (UVLO)
The under voltage lockout feature prevents the controller
from switching when the input voltage is too low to power
the internal power supplies and reference. Hysteresis must
be incorporated in the UVLO comparator to prevent IxR
drops in the wiring or PCB traces from causing ON/OFF
cycling of the controller during heavy loading at power up
or power down.
Overcurrent Protection (OCP)
NCP1597A detects high side switch current and then
compares to a voltage level representing the overcurrent
threshold limit. If the current through the high side FET
exceeds the overcurrent threshold limit for seven
consecutive switching cycles, overcurrent protection is
triggered.
Once the overcurrent protection occurs, hiccup mode
engages. First, hiccup mode, turns off both FETs and
discharges the internal compensation network at the output
of the OTA. Next, the IC waits typically 2 ms and then resets
the overcurrent counter. After this reset, the circuit attempts
another normal softstart. During softstart, the overcurrent
protection threshold is increased to prevent false
overcurrent detection while charging the output capacitors.
Hiccup mode reduces input supply current and power
dissipation during a short circuit. It also allows for much
improved system uptime, allowing autorestart upon
removal of a temporary shortcircuit.
PreBias Startup
In some applications the controller will be required to start
switching when it’s output capacitors are charged anywhere
from slightly above 0 V to just below the regulation voltage.
This situation occurs for a number of reasons: the
converters output capacitors may have residual charge on
them or the converters output may be held up by a low
current standby power supply. NCP1597A supports
prebias start up by holding Low side FETs off till soft start
ramp reaches the FB Pin voltage.
Thermal Shutdown
The NCP1597A protects itself from over heating with an
internal thermal monitoring circuit. If the junction
temperature exceeds the thermal shutdown threshold both
the upper and lower MOSFETs will be shut OFF.
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APPLICATION INFORMATION
Programming the Output Voltage
The output voltage is set using a resistive voltage divider
from the output voltage to FB pin (see Figure 25). So the
output voltage is calculated according to Eq.1.
V
out
+ V
FB
@
R
1
) R
2
R
2
(eq. 1)
Figure 25. Output divider
FB
R2
R1
V
out
Inductor Selection
The inductor is the key component in the switching
regulator. The selection of inductor involves tradeoffs
among size, cost and efficiency. The inductor value is
selected according to the equation 2.
L +
V
out
f @ I
ripple
@ ǒ1 *
V
out
V
in(max)
Ǔ
(eq. 2)
Where V
out
the output voltage;
f switching frequency, 1.0 MHz;
I
ripple
Ripple current, usually it’s 20% 30% of output
current;
V
in(max)
maximum input voltage.
Choose a standard value close to the calculated value to
maintain a maximum ripple current within 30% of the
maximum load current. If the ripple current exceeds this
30% limit, the next larger value should be selected.
The inductors RMS current rating must be greater than
the maximum load current and its saturation current should
be about 30% higher. For robust operation in fault conditions
(startup or short circuit), the saturation current should be
high enough. To keep the efficiency high, the series
resistance (DCR) should be less than 0.1 W, and the core
material should be intended for high frequency applications.
Output Capacitor Selection
The output capacitor acts to smooth the dc output voltage
and also provides energy storage. So the major parameter
necessary to define the output capacitor is the maximum
allowed output voltage ripple of the converter. This ripple is
related to capacitance and the ESR. The minimum
capacitance required for a certain output ripple can be
calculated by Equation 4.
C
OUT(min)
+
I
ripple
8 @ f @ V
ripple
(eq. 3)
Where V
ripple
is the allowed output voltage ripple.
The required ESR for this amount of ripple can be
calculated by equation 5.
ESR +
V
ripple
I
ripple
(eq. 4)
Based on Equation 2 to choose capacitor and check its
ESR according to Equation 3. If ESR exceeds the value from
Eq.4, multiple capacitors should be used in parallel.
Ceramic capacitor can be used in most of the applications.
In addition, both surface mount tantalum and throughhole
aluminum electrolytic capacitors can be used as well.
Maximum Output Capacitor
NCP1597A family has internal 1 ms fixed softstart and
overcurrent limit. It limits the maximum allowed output
capacitor to startup successfully. The maximum allowed
output capacitor can be determined by the equation:
C
out(max)
+
I
lim(min)
* I
load(max)
*
Di
pp
2
V
out
ńT
SS(min)
(eq. 5)
Where T
SS(min)
is the minimum softstart period (1ms);
D
iPP
is the current ripple.
This is assuming that a constant load is connected. For
example, with 3.3 V/2.0 A output and 20% ripple, the max
allowed output capacitors is 546 mF.
Input Capacitor Selection
The input capacitor can be calculated by Equation 6.
C
in(min)
+ I
out(max)
@ D
max
@
1
f @ V
in(ripple)
(eq. 6)
Where V
in(ripple)
is the required input ripple voltage.
D
max
+
V
out
V
in(min)
is the maximum duty cycle.
(eq. 7)
Power Dissipation
The NCP1597A is available in a thermally enhanced
6pin, DFN package. When the die temperature reaches
+185°C, the NCP1597A shuts down (see the
ThermalOverload Protection section). The power
dissipated in the device is the sum of the power dissipated
from supply current (PQ), power dissipated due to switching
the internal power MOSFET (P
SW
), and the power
dissipated due to the RMS current through the internal
power MOSFET (PON). The total power dissipated in the
package must be limited so the junction temperature does
not exceed its absolute maximum rating of +150°C at
NCP1597A
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12
maximum ambient temperature. Calculate the power lost in
the NCP1597A using the following equations:
1. High side MOSFET
The conduction loss in the top switch is:
P
HSON
+ I
2
RMS_HSFET
R
DS(on)HS
(eq. 8)
Where:
I
RMS_FET
+
ǒ
I
out
2
)
DI
PP
2
12
Ǔ
D
Ǹ
(eq. 9)
DI
PP
is the peaktopeak inductor current ripple.
The power lost due to switching the internal power high side
MOSFET is:
P
HSSW
+
V
in
@ I
out
@
ǒ
t
r
) t
f
Ǔ
@ f
SW
2
(eq. 10)
t
r
and t
f
are the rise and fall times of the internal power
MOSFET measured at SW node.
2. Low side MOSFET
The power dissipated in the top switch is:
P
LSON
+ I
RMS_LSFET
2
@ R
DS(on)LS
(eq. 11)
Where:
I
RMS_LSFET
+
ǒ
I
out
2
)
DI
PP
2
12
Ǔ
@
(
1 * D
)
Ǹ
(eq. 12)
DI
PP
is the peaktopeak inductor current ripple.
The switching loss for the low side MOSFET can be
ignored.
The power lost due to the quiescent current (IQ) of the device
is:
P
Q
+ V
in
@ I
Q
(eq. 13)
IQ is the switching quiescent current of the NCP1597A.
P
TOTAL
+ P
HSON
) P
HSSW
) P
LSON
) P
Q
(eq. 14)
Calculate the temperature rise of the die using the following
equation:
T
J
+ T
C
)
ǒ
P
TOTAL
@ q
JC
Ǔ
(eq. 15)
q
JC
is the junctiontocase thermal resistance equal to
1.7°C/W. T
C
is the temperature of the case and TJ is the
junction temperature, or die temperature. The
casetoambient thermal resistance is dependent on how
well heat can be transferred from the PC board to the air.
Solder the undersideexposed pad to a large copper GND
plane. If the die temperature reaches the thermal shutdown
threshold the NCP1597A shut down and does not restart
again until the die temperature cools by 30°C.
Layout Consideration
As with all high frequency switchers, when considering
layout, care must be taken in order to achieve optimal
electrical, thermal and noise performance. For 1.0MHz
switching frequency, switch rise and fall times are typically
in few nanosecond range. To prevent noise both radiated and
conducted the high speed switching current path must be
kept as short as possible. Shortening the current path will
also reduce the parasitic trace inductance of approximately
25 nH/inch. At switch off, this parasitic inductance
produces a flyback spike across the NCP1597A switch.
When operating at higher currents and input voltages, with
poor layout, this spike can generate voltages across the
NCP1597A that may exceed its absolute maximum rating.
A ground plane should always be used under the switcher
circuitry to prevent interplane coupling and overall noise.
The FB component should be kept as far away as possible
from the switch node. The ground for these components
should be separated from the switch current path. Failure to
do so will result in poor stability or subharmonic like
oscillation.
Board layout also has a significant effect on thermal
resistance. Reducing the thermal resistance from ground pin
and exposed pad onto the board will reduce die temperature
and increase the power capability of the NCP1597A. This is
achieved by providing as much copper area as possible
around the exposed pad. Adding multiple thermal vias under
and around this pad to an internal ground plane will also
help. Similar treatment to the inductor pads will reduce any
additional heating effects.

NCP1597AGEVB

Mfr. #:
Manufacturer:
ON Semiconductor
Description:
Power Management IC Development Tools EVB
Lifecycle:
New from this manufacturer.
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