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CAT28LV64GI25

P1-P3P4-P6P7-P9P10-P12P13-P15
CAT28LV64
http://onsemi.com
4
Table 4. CAPACITANCE (T
A
= 25°C, f = 1.0 MHz)
Symbol Test Max Conditions Units
C
I/O
(Note 5) Input/Output Capacitance 10 V
I/O
= 0 V pF
C
IN
(Note 5) Input Capacitance 6 V
IN
= 0 V pF
5. This parameter is tested initially and after a design or process change that affects the parameter.
Table 5. D.C. OPERATING CHARACTERISTICS (V
CC
= 3.0 V to 3.6 V, unless otherwise specified.)
Symbol Parameter Test Conditions
Limits
Units
Min Typ Max
I
CC
V
CC
Current (Operating, TTL) CE = OE = V
IL
,
f = 1/t
RC
min, All I/O’s Open
8 mA
I
SBC
(Note 6) V
CC
Current (Standby, CMOS) CE = V
IHC
, All I/O’s Open 100
mA
I
LI
Input Leakage Current V
IN
= GND to V
CC
−1 1
mA
I
LO
Output Leakage Current V
OUT
= GND to V
CC
,
CE = V
IH
−5 5
mA
V
IH
(Note 6) High Level Input Voltage 2 V
CC
+ 0.3 V
V
IL
Low Level Input Voltage −0.3 0.6 V
V
OH
High Level Output Voltage
I
OH
= −100 mA
2 V
V
OL
Low Level Output Voltage I
OL
= 1.0 mA 0.3 V
V
WI
Write Inhibit Voltage 2 V
6. V
IHC
= V
CC
− 0.3 V to V
CC
+ 0.3 V.
Table 6. A.C. CHARACTERISTICS, READ CYCLE (V
CC
= 3.0 V to 3.6 V, unless otherwise specified.)
Symbol Parameter
28LV64−15 28LV64−20 28LV64−25
Units
Min Max Min Max Min Max
t
RC
Read Cycle Time 150 200 250 ns
t
CE
CE Access Time 150 200 250 ns
t
AA
Address Access Time 150 200 250 ns
t
OE
OE Access Time 70 80 100 ns
t
LZ
(Note 7) CE Low to Active Output 0 0 0 ns
t
OLZ
(Note 7) OE Low to Active Output 0 0 0 ns
t
HZ
(Notes 7, 8) CE High to High−Z Output 50 50 55 ns
t
OHZ
(Notes 7, 8) OE High to High−Z Output 50 50 55 ns
t
OH
(Note 7) Output Hold from Address Change 0 0 0 ns
7. This parameter is tested initially and after a design or process change that affects the parameter.
8. Output floating (High−Z) is defined as the state when the external data line is no longer driven by the output buffer.
CAT28LV64
http://onsemi.com
5
Figure 2. A.C. Testing Input/Output Waveform (Note 9)
INPUT PULSE LEVELS REFERENCE POINTS
2.0 V
0.6 V
0.0 V
V
CC
− 0.3 V
9. Input rise and fall times (10% and 90%) < 10 ns.
Figure 3. A.C. Testing Load Circuit (example)
DEVICE
UNDER
TEST
1.8 K
OUTPUT
1. 3 K
C
L
= 100 pF
C
L
INCLUDES JIG CAPACITANCE
V
CC
Table 7. A.C. CHARACTERISTICS, WRITE CYCLE (V
CC
= 3.0 V to 3.6 V, unless otherwise specified.)
Symbol Parameter
28LV64−15 28LV64−20 28LV64−25
Units
Min Max Min Max Min Max
t
WC
Write Cycle Time 5 5 5 ms
t
AS
Address Setup Time 0 0 0 ns
t
AH
Address Hold Time 100 100 100 ns
t
CS
CE Setup Time 0 0 0 ns
t
CH
CE Hold Time 0 0 0 ns
t
CW
(Note 10) CE Pulse Time 110 150 150 ns
t
OES
OE Setup Time 0 10 10 ns
t
OEH
OE Hold Time 0 10 10 ns
t
WP
(Note 10) WE Pulse Width 110 150 150 ns
t
DS
Data Setup Time 60 100 100 ns
t
DH
Data Hold Time 0 0 0 ns
t
INIT
(Note 11) Write Inhibit Period After
Power−up
5 10 5 10 5 10 ms
t
BLC
(Notes 11, 12)
Byte Load Cycle Time 0.05 100 0.1 100 0.1 100
ms
10.A write pulse of less than 20 ns duration will not initiate a write cycle.
11. This parameter is tested initially and after a design or process change that affects the parameter.
12. A timer of duration t
BLC
max. begins with every LOW to HIGH transition of WE. If allowed to time out, a page or byte write will begin; however
a transition from HIGH to LOW within t
BLC
max. stops the timer.
CAT28LV64
http://onsemi.com
6
DEVICE OPERATION
Read
Data stored in the CAT28LV64 is transferred to the data
bus when WE is held high, and both OE and CE are held low.
The data bus is set to a high impedance state when either CE
or OE goes high. This 2−line control architecture can be used
to eliminate bus contention in a system environment.
Byte Write
A write cycle is executed when both CE and WE are low,
and OE is high. Write cycles can be initiated using either WE
or CE, with the address input being latched on the falling
edge of WE or CE, whichever occurs last. Data, conversely,
is latched on the rising edge of WE or CE, whichever occurs
first. Once initiated, a byte write cycle automatically erases
the addressed byte and the new data is written within 5 ms.
Figure 4. Read Cycle
ADDRESS
DATA OUT DATA VALIDDATA VALID
HIGH−Z
t
OHZ
t
HZ
t
AA
t
OH
t
OE
t
OLZ
t
CE
t
LZ
t
RC
V
IH
CE
OE
WE
Figure 5. Byte Write Cycle [WE Controlled]
CE
OE
WE
ADDRESS
DATA OUT
DATA IN
DATA VALID
HIGH−Z
t
WP
t
OES
t
DS
t
DH
t
BLC
t
OEH
t
CHt
CS
t
AS
t
AH
t
WC
P1-P3P4-P6P7-P9P10-P12P13-P15

CAT28LV64GI25

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