CAT28LV64
http://onsemi.com
7
Page Write
The page write mode of the CAT28LV64 (essentially an
extended BYTE WRITE mode) allows from 1 to 32 bytes of
data to be programmed within a single EEPROM write
cycle. This effectively reduces the byte−write time by a
factor of 32.
Following an initial WRITE operation (WE pulsed low,
for t
WP
, and then high) the page write mode can begin by
issuing sequential WE pulses, which load the address and
data bytes into a 32 byte temporary buffer. The page address
where data is to be written, specified by bits A
5
to A
12
, is
latched on the last falling edge of WE. Each byte within the
page is defined by address bits A
0
to A
4
(which can be loaded
in any order) during the first and subsequent write cycles.
Each successive byte load cycle must begin within t
BLC
MAX
of the rising edge of the preceding WE pulse. There is no
page write window limitation as long as WE is pulsed low
within t
BLC
MAX
.
Upon completion of the page write sequence, WE must
stay high a minimum of t
BLC
MAX
for the internal automatic
program cycle to commence. This programming cycle
consists of an erase cycle, which erases any data that existed
in each addressed cell, and a write cycle, which writes new
data back into the cell. A page write will only write data to
the locations that were addressed and will not rewrite the
entire page.
Figure 6. Byte Write Cycle [CE Controlled]
CE
OE
WE
t
CS
t
OES
ADDRESS
DATA OUT
DATA IN
DATA VALID
HIGH−Z
t
AS
t
CH
t
OEH
t
DH
t
CW
t
AH
t
WC
t
DS
t
BLC
ADDRESS
I/O
BYTE 0 BYTE 1 BYTE 2 BYTE n BYTE n+1 BYTE n+2
LAST BYTE
Figure 7. Page Mode Write Cycle
OE
CE
WE
t
WP
t
BLC
t
WC
