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limit the switching frequency after a load transient as well as to mask PWM comparator output against
noise and spikes.
The system has not an internal clock, because this is a hysteretic controller, so the turn on pulse will start if three
conditions are met contemporarily: the FB pin voltage is lower than the reference voltage, the minimum off time
is passed and the current limit comparator is not triggered (i.e. the inductor current is below the current limit
value). The voltage at the OSC pin must range between 50mV and 1V to ensure the system linearity.
4.2 Closing the loop
The loop is closed connecting the output voltage (or the output divider middle point) to the FB pin. The FB pin
is internally conncted to the comparator negative pin while the positive pin is connected to the reference voltage
(0.6V Typ.) as in Figure 5. When the FB goes lower than the reference voltage, the PWM comparator output
goes high and sets the flip-flop output, turning on the high side MOSFET. This condition is latched to avoid
noise. After the On-Time (calculated as described in the previous section) the system resets the flip-flop, turns
off the high side MOSFET and turns on the low side MOSFET. For more details refers to the Figure 4.
The voltage drop along ground and supply metal paths connecting output capacitor to the load is a source of
DC error. Further the system regulates the output voltage valley value not the average, as shown in Figure 6.
So, the voltage ripple on the output capacitor is a source of DC static error (well as the PCB traces). To com-
pensate the DC errors, an integrator network must be introduced in the control loop, by connecting the output
voltage to the INT pin through a capacitor and the FB pin to the INT pin directly as in Figure 7. The internal in-
tegrator amplifier with the external capacitor C
INT1
introduces a DC pole in the control loop. C
INT1
also provides
an AC path for output ripple.
Figure 6. Valley regulation
The integrator amplifier generates a current, proportional to the DC errors, that increases the output capacitance
voltage in order to compensate the total static error. A voltage clamp within the device forces anINT pin voltage
range (V
REF
-50mV, V
REF
+150mV). This is useful to avoid or smooth output voltage overshoot during a load
transient. Also, this means that the integrator is capable of recovering output error due to ripple when its peak-
to-peak amplitude is less than 150mV in steady state.
In case the ripple amplitude is larger than 150mV, a capacitor C
INT2
can be connected between INT pin and
ground to reduce ripple amplitude at INT pin, otherwise the integrator will operate out of its linear range. Choose
C
INT1
according to the following equation:
(5)
where g
INT
=50 µs is the integrator transconductance,
α
OUT
is the output divider ratio given from Eq4 and F
U
is
the close loop bandwidth. This equation holds if C
INT2
is connected between INT pin and ground. C
INT2
is given
by:
Time
Vout
Vref
<Vout>
DC Error Offset
C
INT1
g
INT
α
OUT
⋅
2 π F
u
⋅⋅
-------------------------------=
