2©2016 Integrated Device Technology, Inc. Revision D, November 7, 2016
840004I-01 Datasheet
Table 1. Pin Descriptions
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
Table 2. Pin Characteristics
Number Name Type Description
1, 20
F_SEL0,
F_SEL1
Input Pullup Frequency select pins. LVCMOS/LVTTL interface levels.
2, 9 nc Unused No connect.
3 nXTAL_SEL Input Pulldown
Selects between the crystal or REF_CLK inputs as the PLL reference
source. When HIGH, selects REF_CLK. When LOW, selects XTAL
inputs. LVCMOS/LVTTL interface levels.
4 REF_CLK Input Pulldown Single-ended reference clock input. LVCMOS/LVTTL interface levels.
5 OE Input Pullup
Output enable pin. When HIGH, the outputs are active. When LOW, the
outputs are in a high impedance state. LVCMOS/LVTTL interface levels.
6 MR Input Pulldown
Active HIGH master reset. When logic HIGH, the internal dividers are
reset causing the outputs to go low. When logic LOW, the internal
dividers and the outputs are enabled. LVCMOS/LVTTL interface levels.
7 nPLL_SEL Input Pulldown
PLL bypass. When LOW, the output is driven from the VCO output.
When HIGH, the PLL is bypassed and the output frequency = reference
clock frequency/N output divider. LVCMOS/LVTTL interface levels.
8V
DDA
Power Analog supply pin.
10 V
DD
Power Core supply pin.
11,
12
XTAL_OUT,
XTAL_IN
Input
Crystal oscillator interface. XTAL_IN is the input. XTAL_OUT is the
output.
13, 19 GND Power Power supply ground.
14, 15, 17, 18 Q3, Q2, Q1, Q0 Output
Single-ended clock outputs. 17
typical output impedance.
LVCMOS/ LVTTL interface levels.
16 V
DDO
Power Output supply pin.
Symbol Parameter Test Conditions Minimum Typical Maximum Units
C
IN
Input Capacitance 4 pF
C
PD
Power Dissipation Capacitance 8 pF
R
PULLUP
Input Pullup Resistor 51 k
R
PULLDOWN
Input Pulldown Resistor 51 k
R
OUT
Output Impedance
V
DDO
= 3.3V±5% 17
V
DDO
= 2.5V±5% 21
