13©2016 Integrated Device Technology, Inc. Revision D, November 7, 2016
840004I-01 Datasheet
Crystal Input Interface
The 840004I-01 has been characterized with 18pF parallel resonant
crystals. The capacitor values shown in Figure 2 below were
determined using a 25MHz, 18pF parallel resonant crystal and were
chosen to minimize the ppm error.
Figure 2. Crystal Input Interface
LVCMOS to XTAL Interface
The XTAL_IN input can accept a single-ended LVCMOS signal
through an AC coupling capacitor. A general interface diagram is
shown in Figure 3. The XTAL_OUT pin can be left floating. The input
edge rate can be as slow as 10ns. For LVCMOS inputs, it is
recommended that the amplitude be reduced from full swing to half
swing in order to prevent signal interference with the power rail and
to reduce noise. This configuration requires that the output
impedance of the driver (Ro) plus the series resistance (Rs) equals
the transmission line impedance. In addition, matched termination at
the crystal input will attenuate the signal in half. This can be done in
one of two ways. First, R1 and R2 in parallel should equal the
transmission line impedance. For most 50 applications, R1 and R2
can be 100. This can also be accomplished by removing R1 and
making R2 50.
Figure 3. General Diagram for LVCMOS Driver to XTAL Input Interface
XTAL_IN
XTAL_OUT
X1
18pF Parallel Crystal
C1
22pF
C2
22pF
XTAL_IN
XTAL_OUT
Ro Rs
Zo = Ro + Rs
50Ω
0.1µf
R1
R2
V
CC
V
CC
14©2016 Integrated Device Technology, Inc. Revision D, November 7, 2016
840004I-01 Datasheet
Schematic Example
Figure 4 shows a schematic example of the 840004I-01. An example
of LVCMOS termination is shown in this schematic. Additional
LVCMOS termination approaches are shown in the LVCMOS
Termination Application Note. In this example, an 18pF parallel
resonant 25MHz crystal is used. The C1= 22pF and C2 = 22pF
are recommended for frequency accuracy. For different board
layouts, the C1 and C2 may be slightly adjusted for optimizing
frequency accuracy. 1k pullup or pulldown resistors can be used for
the logic control input pins.
Figure 4. P.C. 840004I-01 Schematic Example
R5
100
RU1
1K
Zo = 50 Ohm
R4
100
R2
10
Unused outputs can be left floating. There should be
no trace attached to unused outputs. Device
characterized and specification limits set with all
outputs terminated.
VDD
C3
10uF
C1
22pF
RU2
Not Install
RD2
1K
C6
0.1u
XTAL_IN
VDD
If not using the crystal input, it can be left floating.
For additional protection the XTAL_IN pin can be
tied to ground.
Logic Control Input Examples
VDDO
VDD
VDDA
X1
Set Logic
Input to
'1'
U1
840004i_01
1
2
3
4
5
6
7
8
9
10 11
12
13
14
15
16
20
19
18
17
F_SEL0
nc
nXTAL_SEL
REF_CLK
OE
MR
nPLL_SEL
VDDA
nc
VDD XTAL_OUT
XTAL_I N
GND
Q3
Q2
VDDO
F_SEL1
GND
Q0
Q1
VDD
To Logic
Input
pins
LVCMOS
R3
36
RD1
Not Install
C2
22pF
VDD=3.3V
VDD
VDDO=3.3V
To Logic
Input
pins
C5
0.1u
Optional Termination
Zo = 50 Ohm
XTAL_OU T
VDD
C4
0.01u
LVCMOS
Set Logic
Input to
'0'
15©2016 Integrated Device Technology, Inc. Revision D, November 7, 2016
840004I-01 Datasheet
Reliability Information
Table 6.
JA
vs. Air Flow Table for a 20 Lead TSSOP
Transistor Count
The transistor count for 840004I-01: 3796
Package Outline and Package Dimensions
Package Outline - G Suffix for 20 Lead TSSOP Table 7. Package Dimensions for 20 Lead TSSOP
Reference Document: JEDEC Publication 95, MO-153
JA
by Velocity
Linear Feet per Minute 0200500
Single-Layer PCB, JEDEC Standard Test Boards 114.5°C/W 98.0°C/W 88.0°C/W
Multi-Layer PCB, JEDEC Standard Test Boards 73.2°C/W 66.6°C/W 63.5°C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
All Dimensions in Millimeters
Symbol Minimum Maximum
N 20
A 1.20
A1 0.05 0.15
A2 0.80 1.05
b 0.19 0.30
c 0.09 0.20
D 6.40 6.60
E 6.40 Basic
E1 4.30 4.50
e 0.65 Basic
L 0.45 0.75
aaa 0.10

840004BGI-01LFT

Mfr. #:
Manufacturer:
IDT
Description:
Clock Synthesizer / Jitter Cleaner 4-OUTPUT LVCMOS FEMTOCLOCK
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
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