10©2016 Integrated Device Technology, Inc. Revision D, November 7, 2016
840004I-01 Datasheet
Parameter Measurement Information
3.3V Core/3.3V LVCMOS Output Load AC Test Circuit
2.5V Core/2.5V LVCMOS Output Load AC Test Circuit
Output Skew
3.3V Core/2.5V LVCMOS Output Load AC Test Circuit
RMS Phase Jitter
Output Rise/Fall Time
SCOPE
Qx
GND
V
DD,
1.65V±5
-1.65V±5
V
DDO
V
DDA
1.65V±5
SCOPE
Qx
GND
V
DD,
1.25V±5
V
DDO
V
DDA
-1.25V±5
1.25V±5
tsk(o)
V
DDO
2
V
DDO
2
Qx
Qy
SCOPE
Qx
GND
V
DD
1.25V±5
-1.25V±5
V
DDO
V
DDA
2.05V±5
2.05V±5
20%
80%
80%
20%
t
R
t
F
Q0:Q3
11©2016 Integrated Device Technology, Inc. Revision D, November 7, 2016
840004I-01 Datasheet
Parameter Measurement Information, continued
Output Duty Cycle Pulse Width/Period
t
PERIOD
t
PW
t
PERIOD
odc =
V
DDO
2
x 100%
t
PW
Q0:Q3
12©2016 Integrated Device Technology, Inc. Revision D, November 7, 2016
840004I-01 Datasheet
Application Information
Recommendations for Unused Input and Output Pins
Inputs:
Crystal Inputs
For applications not requiring the use of the crystal oscillator input,
both XTAL_IN and XTAL_OUT can be left floating. Though not
required, but for additional protection, a 1k resistor can be tied from
XTAL_IN to ground.
REF_CLK Input
For applications not requiring the use of the reference clock, it can be
left floating. Though not required, but for additional protection, a 1k
resistor can be tied from the REF_CLK to ground.
LVCMOS Control Pins
All control pins have internal pull-downs; additional resistance is not
required but can be added for additional protection. A 1k resistor
can be used.
Outputs:
LVCMOS Outputs
All unused LVCMOS outputs can be left floating. We recommend that
there is no trace attached.
Power Supply Filtering Technique
As in any high speed analog circuitry, the power supply pins are
vulnerable to random noise. To achieve optimum jitter perfor- mance,
power supply isolation is required. The 840004I-01 provides
separate power supplies to isolate any high switching noise from the
outputs to the internal PLL. V
DD,
V
DDA
and V
DDO
should be
individually connected to the power supply plane through vias, and
0.01µF bypass capacitors should be used for each pin. Figure 1
illustrates this for a generic V
DD
pin and also shows that V
DDA
requires that an additional 10 resistor along with a 10F bypass
capacitor be connected to the V
DDA
pin.
Figure 1. Power Supply Filtering
V
DD
V
DDA
3.3V
10Ω
10µF.01µF
.01µF

840004BGI-01LF

Mfr. #:
Manufacturer:
Description:
Clock Synthesizer / Jitter Cleaner 4-OUTPUT LVCMOS FEMTOCLOCK
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
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