4©2016 Integrated Device Technology, Inc. Revision D, November 7, 2016
840004I-01 Datasheet
Table 3C. LVCMOS/LVTTL DC Characteristics, T
A
= -40°C to 85°C
NOTE 1: Outputs terminated with 50 to V
DDO
/2. See Parameter Measurement Information section. Load Test Circuit diagrams.
Table 4. Crystal Characteristics
Symbol Parameter Test Conditions Minimum Typical Maximum Units
V
IH
Input High Voltage
V
DD
= 3.465V 2 V
DD
+ 0.3 V
V
DD
= 2.625V 1.7 V
DD
+ 0.3 V
V
IL
Input Low Voltage
V
DD
= 3.465V -0.3 0.8 V
V
DD
= 2.625V -0.3 0.7 V
I
IH
Input
High Current
nXTAL_SEL,
nPLL_SEL,
REF_CLK, MR
V
DD
= V
IN
= 3.465V or 2.625V 150 µA
OE, F_SEL[0:1] V
DD
= V
IN
= 3.465V or 2.625V 5 µA
I
IL
Input
Low Current
nXTAL_SEL,
nPLL_SEL,
REF_CLK, MR
V
DD
= 3.465V or 2.625V, V
IN
= 0V -5 µA
OE, F_SEL[0:1] V
DD
= 3.465V or 2.625V, V
IN
= 0V -150 µA
V
OH
Output High Voltage; NOTE 1
V
DDO
= 3.3V ± 5% 2.6 V
V
DDO
= 2.5V ± 5% 1.8 V
V
OL
Output Low Voltage; NOTE 1 V
DDO
= 3.3V ± 5% or 2.5V ± 5% 0.5 V
Parameter Test Conditions Minimum Typical Maximum Units
Mode of Oscillation Fundamental
Frequency 25 MHz
Equivalent Series Resistance (ESR) 50
Shunt Capacitance 7pF
Drive Level 1mW
5©2016 Integrated Device Technology, Inc. Revision D, November 7, 2016
840004I-01 Datasheet
AC Electrical Characteristics
Table 5A. AC Characteristics, V
DD
= V
DDO
= 3.3V ± 5%, T
A
= -40°C to 85°C
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device
is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal
equilibrium has been reached under these conditions.
NOTE 1: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at V
DDO
/2.
NOTE 2: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 3: Please refer to the Phase Noise Plot.
Table 5B. AC Characteristics, V
DD
= 3.3V ± 5%, V
DDO
= 2.5V ± 5%, T
A
= -40°C to 85°C
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device
is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal
equilibrium has been reached under these conditions.
NOTE 1: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at V
DDO
/2.
NOTE 2: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 3: Please refer to the Phase Noise Plot.
Parameter Symbol Test Conditions Minimum Typical Maximum Units
f
out
Output Frequency
F_SEL[1:0] = 00 140 156.25 175 MHz
F_SEL[1:0] = 01 or 11 112 125 140 MHz
F_SEL[1:0] = 10 56 62.5 70 MHz
tsk(o) Output Skew: NOTE 1, 2 60 MHz
tjit(Ø)
RMS Phase Jitter (Random);
NOTE 3
156.25MHz, Integration Range:
1.875MHz – 20MHz
0.52 ps
125MHz, Integration Range:
1.875MHz – 20MHz
0.65 ps
62.5MHz, Integration Range:
1.875MHz – 20MHz
0.55 ps
t
R
/ t
F
Output Rise/Fall Time 20% to 80% 250 750 ps
odc Output Duty Cycle
F_SEL[1:0] = 00, 01 or 11 42 58 %
F_SEL[1:0] = 10 49 51 %
Parameter Symbol Test Conditions Minimum Typical Maximum Units
f
out
Output Frequency
F_SEL[1:0] = 00 140 156.25 175 MHz
F_SEL[1:0] = 01 or 11 112 125 140 MHz
F_SEL[1:0] = 10 56 62.5 70 MHz
tsk(o) Output Skew: NOTE 1, 2 60 MHz
tjit(Ø)
RMS Phase Jitter (Random);
NOTE 3
156.25MHz, Integration Range:
1.875MHz – 20MHz
0.48 ps
125MHz, Integration Range:
1.875MHz – 20MHz
0.59 ps
62.5MHz, Integration Range:
1.875MHz – 20MHz
0.53 ps
t
R
/ t
F
Output Rise/Fall Time 20% to 80% 250 750 ps
odc Output Duty Cycle
F_SEL[1:0] = 00, 01 or 11 42 58 %
F_SEL[1:0] = 10 49 51 %
6©2016 Integrated Device Technology, Inc. Revision D, November 7, 2016
840004I-01 Datasheet
Table 5C. AC Characteristics, V
DD
= V
DDO
= 2.5V ± 5%, T
A
= -40°C to 85°C
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the
device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after
thermal equilibrium has been reached under these conditions.
NOTE 1: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at V
DDO
/2.
NOTE 2: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 3: Please refer to the Phase Noise Plot.
Parameter Symbol Test Conditions Minimum Typical Maximum Units
f
out
Output Frequency
F_SEL[1:0] = 00 140 156.25 175 MHz
F_SEL[1:0] = 01 or 11 112 125 140 MHz
F_SEL[1:0] = 10 56 62.5 70 MHz
tsk(o) Output Skew: NOTE 1, 2 60 MHz
tjit(Ø)
RMS Phase Jitter (Random);
NOTE 3
156.25MHz, Integration Range:
1.875MHz – 20MHz
0.50 ps
125MHz, Integration Range:
1.875MHz – 20MHz
0.60 ps
62.5MHz, Integration Range:
1.875MHz – 20MHz
0.51 ps
t
R
/ t
F
Output Rise/Fall Time 20% to 80% 250 750 ps
odc Output Duty Cycle
F_SEL[1:0] = 00, 01 or 11 42 58 %
F_SEL[1:0] = 10 49 51 %

840004BGI-01LF

Mfr. #:
Manufacturer:
Description:
Clock Synthesizer / Jitter Cleaner 4-OUTPUT LVCMOS FEMTOCLOCK
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
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