NLV74HC03ADR2G

© Semiconductor Components Industries, LLC, 2013
October, 2013 Rev. 13
1 Publication Order Number:
MC74HC03A/D
MC74HC03A
Quad 2-Input NAND Gate
with Open-Drain Outputs
HighPerformance SiliconGate CMOS
The MC74HC03A is identical in pinout to the LS03. The device
inputs are compatible with Standard CMOS outputs; with pullup
resistors, they are compatible with LSTTL outputs.
The HC03A NAND gate has, as its outputs, a highperformance
MOS NChannel transistor. This NAND gate can, therefore, with a
suitable pullup resistor, be used in wiredAND applications. Having
the output characteristic curves given in this data sheet, this device can
be used as an LED driver or in any other application that only requires
a sinking current.
Features
Output Drive Capability: 10 LSTTL Loads With Suitable Pullup
Resistor
Outputs Directly Interface to CMOS, NMOS and TTL
High Noise Immunity Characteristic of CMOS Devices
Operating Voltage Range: 2.0 to 6.0 V
Low Input Current: 1 mA
In Compliance With the JEDEC Standard No. 7 A Requirements
Chip Complexity: 28 FETs or 7 Equivalent Gates
NLV Prefix for Automotive and Other Applications Requiring
Unique Site and Control Change Requirements; AECQ100
Qualified and PPAP Capable
These Devices are PbFree, Halogen Free/BFR Free and are RoHS
Compliant
PIN 14 = V
CC
PIN 7 = GND
* Denotes open-drain outputs
LOGIC DIAGRAM
3,6,8,11
Y*
1,4,9,12
A
2,5,10,13
B
OUTPUT
PROTECTION
DIODE
V
CC
Pinout: 14Lead Packages (Top View)
1314 12 11 10 9 8
21 34567
V
CC
B4 A4 Y4 B3 A3 Y3
A1 B1 Y1 A2 B2 Y2 GND
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L
L
H
H
L
H
L
H
FUNCTION TABLE
Inputs Output
AB
Z
Z
Z
L
Y
Z = High Impedance
See detailed ordering and shipping information in the package
dimensions section on page 5 of this data sheet.
ORDERING INFORMATION
MARKING
DIAGRAMS
A = Assembly Location
L, WL = Wafer Lot
Y, YY = Year
W, WW = Work Week
G or G = PbFree Package
TSSOP14
DT SUFFIX
CASE 948G
14
1
SOIC14
D SUFFIX
CASE 751A
14
1
HC03AG
AWLYWW
1
14
HC
03A
ALYWG
G
1
14
(Note: Microdot may be in either location)
MC74HC03A
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2
MAXIMUM RATINGS
Symbol Parameter Value Unit
V
CC
DC Supply Voltage (Referenced to GND) – 0.5 to + 7.0 V
V
in
DC Input Voltage (Referenced to GND) – 0.5 to V
CC
+ 0.5 V
V
out
DC Output Voltage (Referenced to GND) – 0.5 to V
CC
+ 0.5 V
I
in
DC Input Current, per Pin ± 20 mA
I
out
DC Output Current, per Pin ± 25 mA
I
CC
DC Supply Current, V
CC
and GND Pins ± 50 mA
P
D
Power Dissipation in Still Air SOIC Package
TSSOP Package
500
450
mW
T
stg
Storage Temperature –65 to + 150 °C
T
L
Lead Temperature, 1 mm from Case for 10 Seconds
SOIC or TSSOP Package
260
°C
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress
ratings only. Functional operation above the Recommended Operating Conditions is not implied.
Extended exposure to stresses above the Recommended Operating Conditions may affect device
reliability.
Derating SOIC Package: – 7 mW/°C from 65° to 125°C
TSSOP Package: 6.1 mW/°C from 65° to 125°C
RECOMMENDED OPERATING CONDITIONS
Symbol Parameter Min Max Unit
V
CC
DC Supply Voltage (Referenced to GND) 2.0 6.0 V
V
in
, V
out
DC Input Voltage, Output Voltage (Referenced to GND) 0 V
CC
V
T
A
Operating Temperature, All Package Types –55 +125 °C
t
r
, t
f
Input Rise and Fall Time V
CC
= 2.0 V
(Figure 1) V
CC
= 4.5 V
V
CC
= 6.0 V
0
0
0
1000
500
400
ns
DESIGN GUIDE
Criteria Value Unit
Internal Gate Count* 7.0 ea
Internal Gate Propagation Delay 1.5 ns
Internal Gate Power Dissipation 5.0
mW
Speed Power Product 0.0075 pJ
*Equivalent to a twoinput NAND gate
This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this highimpedance cir-
cuit. For proper operation, V
in
and
V
out
should be constrained to the
range GND v (V
in
or V
out
) v V
CC
.
Unused inputs must always be
tied to an appropriate logic voltage
level (e.g., either GND or V
CC
).
Unused outputs must be left open.
MC74HC03A
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3
DC CHARACTERISTICS (Voltages Referenced to GND)
V
CC
V
Guaranteed Limit
Symbol Parameter Condition 55 to 25°C 85°C 125°C Unit
V
IH
Minimum HighLevel Input Voltage V
out
= 0.1V or V
CC
0.1V
|I
out
| 20mA
2.0
3.0
4.5
6.0
1.50
2.10
3.15
4.20
1.50
2.10
3.15
4.20
1.50
2.10
3.15
4.20
V
V
IL
Maximum LowLevel Input Voltage V
out
= 0.1V or V
CC
0.1V
|I
out
| 20mA
2.0
3.0
4.5
6.0
0.50
0.90
1.35
1.80
0.50
0.90
1.35
1.80
0.50
0.90
1.35
1.80
V
V
OL
Maximum LowLevel Output
Voltage
V
out
= 0.1V or V
CC
0.1V
|I
out
| 20mA
2.0
4.5
6.0
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
V
V
in
= V
IH
or V
IL
|I
out
| 2.4mA
|I
out
| 4.0mA
|I
out
| 5.2mA
3.0
4.5
6.0
0.26
0.26
0.26
0.33
0.33
0.33
0.40
0.40
0.40
I
in
Maximum Input Leakage Current V
in
= V
CC
or GND 6.0 ±0.1 ±1.0 ±1.0
mA
I
CC
Maximum Quiescent Supply
Current (per Package)
V
in
= V
CC
or GND
I
out
= 0mA
6.0 1.0 10 40
mA
I
OZ
Maximum ThreeState Leakage
Current
Output in HighImpedance State
V
in
= V
IL
or V
IH
V
out
= V
CC
or GND
6.0 ±0.5 ±5.0 ±10
mA
AC CHARACTERISTICS (C
L
= 50 pF, Input t
r
= t
f
= 6 ns)
V
CC
V
Guaranteed Limit
Symbol Parameter 55 to 25°C 85°C 125°C Unit
t
PLZ
,
t
PZL
Maximum Propagation Delay, Input A or B to Output Y
(Figures 1 and 2)
2.0
3.0
4.5
6.0
120
45
24
20
150
60
30
26
180
75
36
31
ns
t
TLH
,
t
THL
Maximum Output Transition Time, Any Output
(Figures 1 and 2)
2.0
3.0
4.5
6.0
75
27
15
13
95
32
19
16
110
36
22
19
ns
C
in
Maximum Input Capacitance 10 10 10 pF
C
out
Maximum ThreeState Output Capacitance
(Output in HighImpedance State)
10 10 10 pF
C
PD
Power Dissipation Capacitance (Per Buffer)*
Typical @ 25°C, V
CC
= 5.0 V, V
EE
= 0 V
pF
8.0
* Used to determine the noload dynamic power consumption: P
D
= C
PD
V
CC
2
f + I
CC
V
CC
.

NLV74HC03ADR2G

Mfr. #:
Manufacturer:
ON Semiconductor
Description:
Logic Gates QUAD 2-INPUT NAND GA
Lifecycle:
New from this manufacturer.
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