MAX17083
SMPS Detailed Description
Fixed-Frequency,
Current-Mode PWM Controller
The heart of the current-mode PWM controller is a multi-
stage, open-loop comparator that compares the output
voltage-error signal with respect to the reference volt-
age, the current-sense signal, and the slope compensa-
tion ramp (Figure 2). The MAX17083 uses a direct-
summing configuration, approaching ideal cycle-to-
cycle control over the output voltage without a traditional
error amplifier and the phase shift associated with it.
Frequency Selection (FREQ)
The FREQ input selects the PWM mode switching fre-
quency. FREQ is a four-level input to set the regulator
switching frequency. The regulator’s switching frequen-
cy is set according to Table 1, and latched at the
beginning of soft-start. High-frequency (FREQ = V
CC
)
operation optimizes the application for the smallest
component size, trading off efficiency due to higher
switching losses. This might be acceptable in ultra-
portable devices where the load currents are lower.
Low-frequency (FREQ = GND) operation offers the best
overall efficiency at the expense of component size and
board space.
FB Regulation Selection (SET)
The SET input selects one of the four preset feedback
regulation voltage levels. The SET pin is a four-level
input signal to set the FB regulation voltage. The regu-
lator’s feedback regulation voltage is set according to
Table 2, and latched at the beginning of soft-start.
Adjustable Output-Voltage Operation Mode
The MAX17083 produces an adjustable 0.75V to 2.7V
output voltage from the system’s 3.3V or 5V input sup-
ply by using a resistive feedback divider. Set FB to
0.75V (SET = GND) in adjustable mode.
Light-Load Operation
An inherent automatic switchover to pulse-skipping
(PFM operation) takes place at light loads. This
switchover is affected by a comparator that truncates
the low-side switch on-time at the inductor current’s
zero crossing. The zero-crossing comparator senses
the inductor current during the off-time. Once the cur-
rent through the low-side MOSFET drops below 100mA,
the zero-crossing comparator, turns off the low-side
MOSFET. This prevents the inductor from discharging
the output capacitors and forces the switching regula-
tor to skip pulses under light-load conditions to avoid
overcharging the output.
Idle-Mode Current-Sense Threshold
When MAX17083 operates in pulse-skipping mode, the
on-time of the step-down controller terminates when
both the output voltage exceeds the feedback thresh-
old, and the current-sense voltage exceeds the idle-
mode current-sense threshold. Under light-load
conditions, the on-time duration depends solely on the
idle-mode current-sense threshold. This forces the con-
troller to source a minimum amount of power with each
cycle. To avoid overcharging the output, another on-
time cannot be initiated until the output voltage drops
below the feedback threshold. Since the zero-crossing
comparator prevents the switching regulator from sink-
ing current, the MAX17083 switching regulator must
skip pulses. Therefore, the controller regulates the
valley of the output ripple under light-load conditions.
The minimum idle-mode current requirement causes
the threshold between pulse-skipping PFM operation
and constant PWM operation to coincide with the
boundary between continuous and discontinuous
inductor-current operation (also known as the critical
conduction point). The load-current level at which
PFM/PWM crossover occurs (I
LOAD(SKIP)
) is equivalent
to half the idle-mode current threshold (see the
Electrical Characteristics
table for the idle-mode thresh-
old of the regulator). The switching waveforms can
appear noisy and asynchronous at light-load pulse-
skipping operation, but this is a normal operating con-
dition that results in high light-load efficiency.
Trade-offs in PFM noise and light-load efficiency are
made by varying the inductor value. Generally, low
inductor values produce a broader efficiency vs. load
Low-Voltage, Internal Switch,
Step-Down Regulator
10 ______________________________________________________________________________________
FREQ PIN
SELECT
SWITCHING
FREQ, f
SW
SOFT-START
TIME (ms)
1833/f
SW
STARTUP
BLANKING
TIME (ms)
3055/f
SW
V
CC
1.5MHz 1.22 2.0
Open 1MHz 1.83 3.1
REF 750kHz 2.44 4.1
GND 500kHz 3.67 6.1
Table 1. MAX17083 FREQ Table
SET PIN SELECT FB REGULATION VOLTAGE (V)
V
CC
1.8
Open 1.5
REF 1.1
GND 0.75
Table 2. MAX17083 SET Table
MAX17083
Low-Voltage, Internal Switch,
Step-Down Regulator
______________________________________________________________________________________ 11
curve, while higher values result in higher full-load effi-
ciency (assuming that the coil resistance remains fixed)
and less output voltage ripple. Penalties for using high-
er inductor values include larger physical size and
degraded load-transient response (especially at low
input-voltage levels).
SMPS POR, UVLO, and Soft-Start
Power-on reset (POR) occurs when V
CC
rises above
approximately 2.1V, resetting the undervoltage, over-
voltage, and thermal-shutdown fault latches. The V
CC
input undervoltage lockout (UVLO) circuitry prevents
the switching regulators from operating if the 5V bias
supply (V
CC
) is below its 4V UVLO threshold.
Soft-Startup
The internal step-down controller starts switching and the
output voltages ramp up using soft-start. If the bias supply
voltage drops below the UVLO threshold, the controller
stops switching and disables the drivers (LX becomes
high impedance) until the bias supply voltage recovers.
Once the 5V bias supply and IN rise above their respec-
tive input UVLO thresholds, and EN is pulled high, the
internal step-down controller becomes enabled and
begins switching. The internal voltage soft-starts gradu-
ally increment the feedback voltage by approximately
25mV every 61 switching cycles. Therefore, OUT reach-
es its nominal regulation voltage 1833/f
SW
after the regu-
lator is enabled (see the Soft-Start Waveforms in the
Typical Operating Characteristics
section
)
.
SMPS Power-Good Output (POK)
POK is the open-drain output of the window comparator
that continuously monitors the output for undervoltage
and overvoltage conditions. POK is actively held low in
shutdown (EN = GND) and during soft-start. Once the
soft-start sequence terminates, POK becomes high
impedance as long as the output remains within ±10%
of the nominal regulation voltage set by FB. POK goes
low once the output drops 12% (typ) below or rises 12%
(typ) above its nominal regulation point, or the output is
shut down. For a logic-level POK output voltage, con-
nect an external pullup resistor between POK and V
CC
.
A 100kΩ pullup resistor works well in most applications.
SMPS Fault Protection
Output Overvoltage Protection (OVP)
If the output voltage rises above 112% (typ) of its nomi-
nal regulation voltage, the controller sets the fault latch,
pulls POK low, shuts down the regulator, and immedi-
ately pulls the output to ground through its low-side
MOSFET. Turning on the low-side MOSFET with 100%
duty cycle rapidly discharges the output capacitors and
clamps the output to ground. However, this commonly
undamped response causes negative output voltages
due to the energy stored in the output LC at the instant
of 0V fault. If the load cannot tolerate a negative voltage,
place a power Schottky diode across the output to act
as a reverse-polarity clamp. If the condition that caused
the overvoltage persists (such as a shorted high-side
MOSFET), the input source also fails (short-circuit fault).
Cycle V
CC
below 1V or toggle the enable input to clear
the fault latch and restart the regulator.
Output Undervoltage Protection (UVP)
Each MAX17083 includes an output undervoltage
(UVP) protection circuit that begins to monitor the out-
put once the startup blanking period has ended. If the
output voltage drops below 88% (typ) of its nominal
regulation voltage, the regulator pulls the POK output
low and begins the UVP fault timer. Once the timer
expires after 1600/f
SW
, the regulator shuts down, forc-
ing the high-side off and disabling the low-side MOS-
FET once the zero-crossing threshold has been
reached. Cycle V
CC
below 1V, or toggle the enable
input to clear the fault latch and restart the regulator.
Thermal-Fault Protection
The MAX17083 features a thermal-fault protection
circuit. When the junction temperature rises above
+160°C (typ), a thermal sensor activates the fault latch,
pulls down the POK output, and shuts down the regu-
lator. Toggle EN to clear the fault latch, and restart the
controllers after the junction temperature cools by
15°C (typ).
SMPS Design Procedure
(Step-Down Regulator)
Firmly establish the input voltage range and maximum
load current before choosing a switching frequency
and inductor operating point (ripple-current ratio). The
primary design trade-off lies in choosing a good switch-
ing frequency and inductor operating point, and the fol-
lowing four factors dictate the rest of the design:
Input Voltage Range. The maximum value (V
IN(MAX)
),
and minimum value (V
IN(MIN)
) must accommodate
the worst-case conditions accounting for the input
voltage soars and drops. If there is a choice at all,
lower input voltages result in better efficiency.
Maximum Load Current. There are two values to
consider. The peak load current (I
LOAD(MAX)
) deter-
mines the instantaneous component stresses and fil-
tering requirements and thus drives output-capacitor
selection, inductor-saturation rating, and the design of
the current-limit circuit. The continuous load current
(I
LOAD
) determines the thermal stresses and thus dri-
ves the selection of input capacitors, MOSFETs, and
other critical heat-contributing components.
Switching Frequency. This choice determines the
basic trade-off between size and efficiency. The
optimal frequency is largely a function of maximum
input voltage due to MOSFET switching losses that
are proportional to frequency and the square of V
IN
.
The optimum frequency is also a moving target, due
to rapid improvements in MOSFET technology that
are making higher frequencies more practical.
Inductor Operating Point. This choice provides
trade-offs between size and efficiency, and
between transient response and output ripple. Low
inductor values provide better transient response
and smaller physical size, but also result in lower
efficiency and higher output ripple due to increased
ripple currents. The minimum practical inductor
value is one that causes the circuit to operate at the
edge of critical conduction (where the inductor cur-
rent just touches zero with every cycle at maximum
load). Inductor values lower than this grant no fur-
ther size-reduction benefit. The optimum operating
point is usually found between 20% and 50% of rip-
ple current. When pulse skipping (at light loads),
the inductor value also determines the load-current
value at which PFM/PWM switchover occurs.
Step-Down Inductor Selection
The switching frequency and inductor operating point
determine the inductor value as follows:
Assuming 5A maximum load current, and an LIR of 0.3
yields:
Find a low-loss inductor having the lowest possible DC
resistance that fits in the allotted dimensions. Most
inductor manufacturers provide inductors in standard
values, such as 1.0µH, 1.5µH, 2.2µH, 3.3µH, etc. Also
look for nonstandard values, which can provide a better
compromise in LIR across the input voltage range. If
using a swinging inductor (where the no-load induc-
tance decreases linearly with increasing current), evalu-
ate the LIR with properly scaled inductance values. For
the selected inductance value, the actual peak-to-peak
inductor ripple current (ΔI
INDUCTOR
) is defined by:
Ferrite cores are often the best choice, although soft sat-
urating molded core inductors are inexpensive and can
work well at 500kHz. The core must be large enough not
to saturate at the peak inductor current (I
PEAK
):
SMPS Output-Capacitor Selection
The output filter capacitor selection requires careful
evaluation of several different design requirements—
stability, transient response, and output ripple volt-
age—that place limits on the output capacitance and
ESR. Based on these requirements, the typical applica-
tion requires a low-ESR polymer capacitor (lower cost
but higher output-ripple voltage) or bulk ceramic
capacitors (higher cost but low output-ripple voltage).
SMPS Loop Compensation
Voltage positioning dynamically lowers the output volt-
age in response to the load current, reducing the loop
gain. This reduces the output capacitance requirement
(stability and transient) and output power dissipation
requirements as well. The load-line is generated by
sensing the inductor current through the high-side
MOSFET on-resistance, and is internally preset to
-5mV/A (typ). The load-line ensures that the output volt-
age remains within the regulation window over the full-
load conditions.
The load line of the internal SMPS regulators also pro-
vides the AC ripple voltage required for stability. To
maintain stability, the output capacitive ripple must be
kept smaller than the internal AC ripple voltage, and
crossover must occur before the Nyquist pole occurs
(1 + duty)/(2f
SW
). Based on these loop requirements, a
minimum output capacitance can be determined from
the following:
where R
DROOP
is 5mV/A as defined in the
Electrical
Characteristics
table and f
SW
is the switching frequen-
cy selected by the FREQ setting (see Table 1).
C
fR
V
V
V
V
OUT
SW DROOP
REF
OUT
OUT
>
+
1
2
1
IIN
ΔI
VVV
Vf L
INDUCTOR
OUT IN OUT
IN OSC
=
()
-
L
VVV
Vf
OUT IN OUT
IN OSC
=
×
()
××
-
15.
L
VVV
Vf I LIR
OUT IN OUT
IN OSC LOAD MAX
=
×
()
×× ×
-
()
MAX17083
Low-Voltage, Internal Switch,
Step-Down Regulator
12 ______________________________________________________________________________________

MAX17083ETG+T

Mfr. #:
Manufacturer:
Maxim Integrated
Description:
Switching Voltage Regulators Low-Voltage Internal Switch Step-Down
Lifecycle:
New from this manufacturer.
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