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KA555IDTF

P1-P3P4-P6P7-P9P10-P12P13-P14
KA555
KA555KA555
KA555
4
44
4
Application Information
Application InformationApplication Information
Application Information
Table1 below is the basic operating table of 555 timer:
When the low signal input is applied to the reset terminal, the timer output remains low regardless of the threshold voltage or
the trigger voltage. Only when the high signal is applied to the reset terminal, the timer's output changes according to
threshold voltage and trigger voltage.
When the threshold voltage exceeds 2/3 of the supply voltage while the timer output is high, the timer's internal discharge Tr.
turns on, lowering the threshold voltage to below 1/3 of the supply voltage. During this time, the timer output is maintained
low. Later, if a low signal is applied to the trigger voltage so that it becomes 1/3 of the supply voltage, the timer's internal
discharge Tr. turns off, increasing the threshold voltage and driving the timer output again at high.
1. MonoStable Operation
1. MonoStable Operation1. MonoStable Operation
1. MonoStable Operation
Table 1. Basic Operating Table
Table 1. Basic Operating TableTable 1. Basic Operating Table
Table 1. Basic Operating Table
Threshold Voltage
Threshold Voltage Threshold Voltage
Threshold Voltage
(V
(V(V
(V
th
thth
th
)(Pin6)
)(Pin6))(Pin6)
)(Pin6)
Trigger Voltage
Trigger VoltageTrigger Voltage
Trigger Voltage
(V
(V(V
(V
tr
trtr
tr
)(Pin2)
)(Pin2))(Pin2)
)(Pin2)
Reset(Pin4)
Reset(Pin4)Reset(Pin4)
Reset(Pin4) Output(Pin3)
Output(Pin3)Output(Pin3)
Output(Pin3)
Discharging Tr.
Discharging Tr.Discharging Tr.
Discharging Tr.
(Pin7)
(Pin7)(Pin7)
(Pin7)
Don't care Don't care Low Low ON
V
th
> 2Vcc / 3 V
th
> 2Vcc / 3 High Low ON
Vcc / 3 < V
th
< 2 Vcc / 3 Vcc / 3 < V
th
< 2 Vcc / 3 High - -
V
th
< Vcc / 3 V
th
< Vcc / 3 High High OFF
10
1010
10
-5
-5-5
-5
10
1010
10
-4
-4-4
-4
10
1010
10
-3
-3-3
-3
10
1010
10
-2
-2-2
-2
10
1010
10
-1
-1-1
-1
10
1010
10
0
00
0
10
1010
10
1
11
1
10
1010
10
2
22
2
10
1010
10
-3
-3-3
-3
10
1010
10
-2
-2-2
-2
10
1010
10
-1
-1-1
-1
10
1010
10
0
00
0
10
1010
10
1
11
1
10
1010
10
2
22
2
10M
10M10M
10M
Ω
ΩΩ
Ω
1M
1M1M
1M
Ω
ΩΩ
Ω
10k
10k10k
10k
Ω
ΩΩ
Ω
100k
100k100k
100k
Ω
ΩΩ
Ω
R
RR
R
A
AA
A
=1k
=1k=1k
=1k
Ω
ΩΩ
Ω
Capacitance(uF)
Capacitance(uF)Capacitance(uF)
Capacitance(uF)
Time Delay(s)
Time Delay(s)Time Delay(s)
Time Delay(s)
Figure 1. Monoatable Circuit
Figure 1. Monoatable CircuitFigure 1. Monoatable Circuit
Figure 1. Monoatable Circuit
Figure 2. Resistance and Capacitance vs.
Figure 2. Resistance and Capacitance vs.Figure 2. Resistance and Capacitance vs.
Figure 2. Resistance and Capacitance vs.
Time delay(t
Time delay(tTime delay(t
Time delay(t
d
dd
d
)
))
)
Figure 3. Waveforms of Monostable Operation
Figure 3. Waveforms of Monostable OperationFigure 3. Waveforms of Monostable Operation
Figure 3. Waveforms of Monostable Operation
1
5
6
7
8
4
2
3
RESET
Vcc
DISCH
THRES
CONT
GND
OUT
TRIG
+Vcc
R
A
C1
C2R
L
Trigger
KA555
KA555KA555
KA555
5
55
5
Figure 1 illustrates a monostable circuit. In this mode, the timer generates a fixed pulse whenever the trigger voltage falls
below Vcc/3. When the trigger pulse voltage applied to the #2 pin falls below Vcc/3 while the timer output is low, the timer's
internal flip-flop turns the discharging Tr. off and causes the timer output to become high by charging the external capacitor C1
and setting the flip-flop output at the same time.
The voltage across the external capacitor C1, V
C1
increases exponentially with the time constant t=R
A
*C and reaches 2Vcc/3
at td=1.1R
A
*C. Hence, capacitor C1 is charged through resistor R
A
. The greater the time constant R
A
C, the longer it takes
for the V
C1
to reach 2Vcc/3. In other words, the time constant R
A
C controls the output pulse width.
When the applied voltage to the capacitor C1 reaches 2Vcc/3, the comparator on the trigger terminal resets the flip-flop,
turning the discharging Tr. on. At this time, C1 begins to discharge and the timer output converts to low.
In this way, the timer operating in the monostable repeats the above process. Figure 2 shows the time constant relationship
based on R
A
and C. Figure 3 shows the general waveforms during the monostable operation.
It must be noted that, for a normal operation, the trigger pulse voltage needs to maintain a minimum of Vcc/3 before the timer
output turns low. That is, although the output remains unaffected even if a different trigger pulse is applied while the output is
high, it may be affected and the waveform does not operate properly if the trigger pulse voltage at the end of the output pulse
remains at below Vcc/3. Figure 4 shows such a timer output abnormality.
2. Astable Operation
2. Astable Operation2. Astable Operation
2. Astable Operation
Figure 4. Waveforms of Monostable Operation (abnormal)
Figure 4. Waveforms of Monostable Operation (abnormal)Figure 4. Waveforms of Monostable Operation (abnormal)
Figure 4. Waveforms of Monostable Operation (abnormal)
100m
100m100m
100m 1
11
110
1010
10 100
100100
100 1k
1k1k
1k 10k
10k10k
10k 100k
100k100k
100k
1E-3
1E-31E-3
1E-3
0.01
0.010.01
0.01
0.1
0.10.1
0.1
1
11
1
10
1010
10
100
100100
100
10M
10M10M
10M
Ω
ΩΩ
Ω
1M
1M1M
1M
Ω
ΩΩ
Ω
100k
100k100k
100k
Ω
ΩΩ
Ω
10k
10k10k
10k
Ω
ΩΩ
Ω
1k
1k1k
1k
Ω
ΩΩ
Ω
(R
(R(R
(R
A
AA
A
+2R
+2R+2R
+2R
B
BB
B
)
))
)
Capacitance(uF)
Capacitance(uF)Capacitance(uF)
Capacitance(uF)
Frequency(Hz)
Frequency(Hz)Frequency(Hz)
Frequency(Hz)
Figure 5. Astable Circuit
Figure 5. Astable CircuitFigure 5. Astable Circuit
Figure 5. Astable Circuit
Figure 6. Capacitance and Resistance vs. Frequency
Figure 6. Capacitance and Resistance vs. FrequencyFigure 6. Capacitance and Resistance vs. Frequency
Figure 6. Capacitance and Resistance vs. Frequency
1
5
6
7
8
4
2
3
RESET
Vcc
DISCH
THRES
CONT
GND
OUT
TRIG
+Vcc
R
A
C1
C2R
L
R
B
KA555
KA555KA555
KA555
6
66
6
An astable timer operation is achieved by adding resistor R
B
to Figure 1 and configuring as shown on Figure 5. In the astable
operation, the trigger terminal and the threshold terminal are connected so that a self-trigger is formed, operating as a multi
vibrator. When the timer output is high, its internal discharging Tr. turns off and the V
C1
increases by exponential
function with the time constant (R
A
+R
B
)*C.
When the V
C1
, or the threshold voltage, reaches 2Vcc/3, the comparator output on the trigger terminal becomes high,
resetting the F/F and causing the timer output to become low. This in turn turns on the discharging Tr. and the C1 discharges
through the discharging channel formed by R
B
and the discharging Tr. When the V
C1
falls below Vcc/3, the comparator
output on the trigger terminal becomes high and the timer output becomes high again. The discharging Tr. turns off and the
V
C1
rises again.
In the above process, the section where the timer output is high is the time it takes for the V
C1
to rise from Vcc/3 to 2Vcc/3,
and the section where the timer output is low is the time it takes for the V
C1
to drop from 2Vcc/3 to Vcc/3. When timer output
is high, the equivalent circuit for charging capacitor C1 is as follows:
Since the duration of the timer output high state(t
H
) is the amount of time it takes for the V
C1
(t) to reach 2Vcc/3,
Figure 7. Waveforms of Astable Operation
Figure 7. Waveforms of Astable OperationFigure 7. Waveforms of Astable Operation
Figure 7. Waveforms of Astable Operation
Vcc
R
A
R
B
C1 Vc1(0-)=Vcc/
3
C
1
dv
C1
dt
−−−−−−−−−
V
CC
V0-()–
R
A
R
B
+
−−−−−−−−−−−−−−−−−−−−
= 1()
V
C1
0+()V
CC
3⁄= 2()
V
C1
t() V
CC
1
2
3
−−e– -
t
R
A
R
B
+()C1
−−−−−−−−−−−−−−−−−−−−−−


–


= 3()
P1-P3P4-P6P7-P9P10-P12P13-P14

KA555IDTF

Mfr. #:
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Manufacturer:
ON Semiconductor / Fairchild
Description:
Timers & Support Products Single Timer
Lifecycle:
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