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KA555IDTF

P1-P3P4-P6P7-P9P10-P12P13-P14
KA555
KA555KA555
KA555
7
77
7
The equivalent circuit for discharging capacitor C1, when timer output is low, is as follows:
Since the duration of the timer output low state(
t
L
) is the amount of time it takes for the V
C1
(t) to reach Vcc/3,
Since R
D
is normally R
B
>> R
D
although related to the size of discharging Tr.,
t
L
=0.693R
B
C
1
(10)
Consequently, if the timer operates in astable, the period is the same with
'T=t
H
+t
L
=0.693(RA+R
B
)C
1
+0.693R
B
C
1
=0.693(R
A
+2R
B
)C
1
' because the period is the sum of the charge time and discharge
time. And since frequency is the reciprocal of the period, the following applies.
3. Frequency divider
3. Frequency divider3. Frequency divider
3. Frequency divider
By adjusting the length of the timing cycle, the basic circuit of Figure 1 can be made to operate as a frequency divider. Figure
8. illustrates a divide-by-three circuit that makes use of the fact that retriggering cannot occur during the timing cycle.
V
C1
t()
2
3
−−V
CC
V
CC
1
2
3
−−e– -
t
H
R
A
R
B
+()C1
−−−−−−−−−−−−−−−−−−−−−−



–



== 4()
t
H
C
1
R
A
R
B
+()In2 0.693 R
A
R
B
+()C
1
== 5()
C1
R
B
R
D
V
C1
(0-)=2Vcc/3
C
1
dv
C1
dt
−−−−−−−−−
1
R
A
R
B
+
−−−−−−−−−−−−−−V
C1
0=+ 6()
V
C1
t()
2
3
−−V
CC
e
-
t
R
A
R
D
+()C1
−−−−−−−−−−−−−−−−−−−−−−
= 7()
1
3
---V
CC
2
3
---V
CC
e
=
t
L
R
A
R
D
+()C1
-------------------------------------
– (8)
t
L
C
1
R
B
R
D
+()In2 0.693 R
B
R
D
+()C
1
== (9)
frequency, f
1
T
−−
1.44
R
A
2R
B
+()C
1
−−−−−−−−−−−−−−−−−−−−−−−−
== 11()
KA555
KA555KA555
KA555
8
88
8
4. Pulse Width Modulation
4. Pulse Width Modulation4. Pulse Width Modulation
4. Pulse Width Modulation
The timer output waveform may be changed by modulating the control voltage applied to the timer's pin 5 and changing the
reference of the timer's internal comparators. Figure 9 illustrates the pulse width modulation circuit.
When the continuous trigger pulse train is applied in the monostable mode, the timer output width is modulated according to
the signal applied to the control terminal. Sine wave as well as other waveforms may be applied as a signal to the control
terminal. Figure 10 shows the example of pulse width modulation waveform.
5. Pulse Position Modulation
5. Pulse Position Modulation5. Pulse Position Modulation
5. Pulse Position Modulation
If the modulating signal is applied to the control terminal while the timer is connected for the astable operation as in Figure 11,
the timer becomes a pulse position modulator.
In the pulse position modulator, the reference of the timer's internal comparators is modulated which in turn modulates the
timer output according to the modulation signal applied to the control terminal.
Figure 12 illustrates a sine wave for modulation signal and the resulting output pulse position modulation : however, any wave
shape could be used.
Figure 8. Waveforms of Frequency Divider Operation
Figure 8. Waveforms of Frequency Divider OperationFigure 8. Waveforms of Frequency Divider Operation
Figure 8. Waveforms of Frequency Divider Operation
84
7
1
2
3
5
6
CONT
GND
Vcc
DISCH
THRES
RESET
TRIG
OUT
+Vcc
+Vcc+Vcc
+Vcc
Trigger
TriggerTrigger
Trigger
R
RR
R
A
AA
A
C
CC
C
Output
OutputOutput
Output
Input
InputInput
Input
Figure 9. Circuit for Pulse Width Modulation
Figure 9. Circuit for Pulse Width ModulationFigure 9. Circuit for Pulse Width Modulation
Figure 9. Circuit for Pulse Width Modulation
Figure 10. Waveforms of Pulse Width Modulation
Figure 10. Waveforms of Pulse Width ModulationFigure 10. Waveforms of Pulse Width Modulation
Figure 10. Waveforms of Pulse Width Modulation
KA555
KA555KA555
KA555
9
99
9
6. Linear Ramp
6. Linear Ramp6. Linear Ramp
6. Linear Ramp
When the pull-up resistor RA in the monostable circuit shown in Figure 1 is replaced with constant current source, the V
C1
increases linearly, generating a linear ramp. Figure 13 shows the linear ramp generating circuit and Figure 14 illustrates the
generated linear ramp waveforms.
In Figure 13, current source is created by PNP transistor Q1 and resistor R1, R2, and R
E
.
For example, if Vcc=15V, R
E
=20kΩ, R1=5kW, R2=10kΩ, and V
BE
=0.7V,
V
E
=0.7V+10V=10.7V
Ic=(15-10.7)/20k=0.215mA
When the trigger starts in a timer configured as shown in Figure 13, the current flowing through capacitor C1 becomes a
84
7
1
2
3
5
6
CONT
GND
Vcc
DISCH
THRES
RESET
TRIG
OUT
+Vcc
+Vcc+Vcc
+Vcc
R
RR
R
A
AA
A
C
CC
C
R
RR
R
B
BB
B
Modulation
ModulationModulation
Modulation
Output
OutputOutput
Output
Figure 11. Circuit for Pulse Position Modulation
Figure 11. Circuit for Pulse Position ModulationFigure 11. Circuit for Pulse Position Modulation
Figure 11. Circuit for Pulse Position Modulation
Figure 12. Waveforms of pulse position modulation
Figure 12. Waveforms of pulse position modulationFigure 12. Waveforms of pulse position modulation
Figure 12. Waveforms of pulse position modulation
Figure 13. Circuit for Linear Ramp
Figure 13. Circuit for Linear RampFigure 13. Circuit for Linear Ramp
Figure 13. Circuit for Linear Ramp
Figure 14. Waveforms of Linear Ramp
Figure 14. Waveforms of Linear RampFigure 14. Waveforms of Linear Ramp
Figure 14. Waveforms of Linear Ramp
1
5
6
7
8
4
2
3
RESET
Vcc
DISCH
THRES
CONT
GND
OUT
TRIG
+Vcc
C2
R1
R2
C1
Q1
Output
R
E
I
C
V
CC
V
E
–
R
E
−−−−−−−−−−−−−−−−
= 12()
Here, V
E is
V
E
V
BE
R
2
R
1
R
2
+
−−−−−−−−−−−−−V
CC
+= 13()
P1-P3P4-P6P7-P9P10-P12P13-P14

KA555IDTF

Mfr. #:
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Manufacturer:
ON Semiconductor / Fairchild
Description:
Timers & Support Products Single Timer
Lifecycle:
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