ASAHI KASEI [AK2301A]
<MS0300-E-01> 13 2005/8
FUNCTIONAL DESCRIPTIONS
PCM CODEC
- A/D
Analog input signal is converted to 14bit PCM data. The analog signal is fed to the anti-aliasing filter
(AAF) before the converting PCM data, to prevent signals around the sampling rate from folding back
into the voice band. The converted PCM data passes through the band limiting filter which Frequency
response is designated in page8, and output from the DX pin with MSB first format. It is synchronized
with rising edge of the BCLK. This PCM data is 2’s compliment 2digit data and full scale is defined as
3.14dBm0. The analog input of 0.762Vrms is converted to a digital code of 3.14dBm0.
- D/A
Input PCM data from the DR pin is through the digital filter which Frequency response is designated in page8,
and converted analog signal. This analog signal is removed the high frequency element with SMF (fc=30kHz
typ) and output from the VR pin. The input PCM data is 2’s compliment 2digit data and full scale is defined as
3.14dBm0. When the input signal is 3.14dBm0, the level of the analog output signal becomes 0.762Vrms.
- PCM digital code
The relation ship between the analog signal and the 14bit linear code.
Signal level 14bit linear CODE (MSB First)
+Full code 01 1111 1111 1111
Peak value of the PCM 0dBm0 CODEC 01 0110 0100 1010
PCM 0-CODE 00 0000 0000 0000
-Full scale 10 0000 0000 0000
ASAHI KASEI [AK2301A]
<MS0300-E-01> 14 2005/8
PCM Data Interface
AK2301A supports the following 2 PCM data formats
- Long Frame Sync (LF)
- Short Frame Sync (SF)
PCM data is interfaced through the pin (DX, DR).
In each case, PCM data is interfaced by the 2’s compliment 2digit data with 16bit MSB first format. However,
internal CODEC is 14bit format operation, then the lowest 2bits output become to “L” level. For the input, the
lowest 2bits are ignored.
Selection of the interface format
The AK2301A automatically selects the Long Frame/Short frame by means of detecting the length frame
signal.
LONG FRAME (LF) / SHORT FRAME (SF)
-Automatic LF/SF detection
AK2301A monitors the duration of the “H” level of FS and automatically selects LF or SF interface
format.
Period of FS=”H” Frame type
More than 2 clocks of BCLK
LF
1 clock of BCLK SF
Timing of the interface
16bit PCM data is accommodated in 1 flame (125µs) defined by 8kHz frame sync signal. Although there are
4time slot at maximum in 8kHz frame (when BCLK = 512kHz), PCM data for AK2301A occupies first time
slot.
ASAHI KASEI [AK2301A]
<MS0300-E-01> 15 2005/8
- Frame sync signal FS
8kHz reference signal. This signal indicated the timing and the frame position of 8kHz PCM interface.
All the internal clock of the LSI is generated based on this FS signal.
-Bit clock BCLK
BCLK defines the PCM data rate. BCLK rate is 256kHz or 512kHz. This clock must be synchronized with FS.
LongFrame
FS
DX
DR
BCLK
Don
t
care
Don
t care
1
2
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7
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5
6
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L
L
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ShortFrame
FS
DX
DR
BCLK
D
on
t
care
Don
t care
1
2
3
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7
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5
6
1
2
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L
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Important notice!
Please don’t stop feeding FS and BCLK.
Both FS and BCLK is used as the internal reference clock. LSI does not work when the FS and BCLK are not
provided.
When stop the BCLK and FS, please set RSTN=“L”.

AK2301A

Mfr. #:
Manufacturer:
Description:
IC PCM CODEC LSI 1CH 3V 24VSOP
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
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