ASAHI KASEI [AK2301A]
<MS0300-E-01> 4 2005/8
PIN FUNCTION
Pin types
NIN: Normal input TOUT: Try state output PWR: Power / Ground
AIN: Analog input AOUT: Analog output
Pin# Name Type
Function
15 VFTN
AIN
Negative analog onput of transmit OP amp.
Diffelential or signal amplifire is composed with the VFTP and the exernal
registers. Transmit gain is defined by the ratio of the external registers.
16 VFTP AIN
Positive analog input of the transmit OP amp.
14 GST AOUT
Output of the transmit OP amp.
The external feedback resister is connected between this pin and VFTP.
7 GSR AOUT
Output of the receive OP amp.
Receive gain is defined by the ratio of the external registers.
The differential output can be composed with using the VR.
8 VFR AIN
Negative analog input of the receive OP amp.
9 VR AOUT
Analog output of the D/A converter equivalent to the received PCM code.
6 VDD PWR
Positive supply voltage
+3.3V supply
19 VSS PWR
Ground (0V)
5 FS NIN
Frame sync input
This clock is input for the internal PLL which generates the internal system
clocks. FS must be 8kHz clock which synchronized with BCLK and do not
stop feeding. *
3 BCLK NIN
Bit clock of PCM data interface
This clock defines the input/output timing of DX and RX.
The frequency of BCLK should be 256kHz or 512kHz and do not stop
feeding. *
2 DX TOUT
Serial output of PCM data
The PCM data is synchronized with BCLK. This output remains in the high
impedance except for the period in which PCM data is transmitted.
4 DR NIN
Serial input of PCM data
The PCM data is synchronized with BCLK.
23 MUTEN NIN
Mute setting pin
“L” level forces both A/D, D/A output to mute state.
22 RSTN NIN
Reset signal input pin
Reset operation starts by low input. This pin is used for the initialization at
the power up.Please use MUTEN pin together to avoid the popping sound
output until the LSI finish the initialization after the power up. (Refer to P.13)
18 VREF AOUT
Analog ground output
External capacitance (1.0µF or more) should be connected between this pin
and VSS. Please do not connect external load to this pin.
20 PLLC AOUT
PLL loop filter output
External capacitance (0.33µF±40%: Includes temperature characteristic)
should be connected between this pin and VSS.
17 TAGND AIN
Analog ground output for transmit OP amp
150µA load max. External capacitance (1.0µ
F or more) should be connected
between this pin and VSS. This pin is used as an analog ground for transmit
OP amp (AMPT).
12
11
AMP1I
AMP2I
AIN
Negative input of the universal OP amp
13
10
AMP1O
AMP2O
AOUT
Output of the universal OP amp
21
24
1
TEST1
TEST2
TEST3
NIN
Test pins (“H”=test mode)
Please tie to VSS
*) When stop the BCLK and FS, please set RSTN=“L”.
