MAX6952
4-Wire Interfaced, 2.7V to 5.5V,
4-Digit 5
7 Matrix LED Display Driver
______________________________________________________________________________________ 13
Table 18 shows an example of data (characters 0, 1,
and 2) being stored in the first three user-defined font
locations, illustrating the orientation of the data bits.
Table 19 shows the six sequential write commands
required to set a MAX6953's font character RAM02 with
the data to display character 2 given in the font RAM
illustration above.
Multiplex Clock and Blink Timing
The OSC pin can be fitted with capacitor C
SET
to GND
(to use the internal RC multiplex oscillator), or driven by
an external clock. The multiplex clock frequency deter-
mines the multiplex scan rate and the blink timing. The
display scan rate is calculated by dividing the frequency
at OSC by 5600. With OSC at 4 MHz, each display digit
is enabled for 100µs and the display scan rate is
714.29Hz.
The on-chip oscillator may be accurate enough for
applications using a single device. If an exact blink rate
is required, use an external clock ranging between
1MHz and 8MHz to drive OSC. The OSC inputs of multi-
ple MAX6952s can be tied together to a common exter-
nal clock to make the devices blink at the same rate.
The relative blink phasing of multiple MAX6952s can be
synchronized by setting the T bit in the control register
for all the devices in quick succession (Table 11).
If the serial interfaces of multiple MAX6952s are daisy-
chained by connecting DOUT of one device to DIN of
the next, then synchronization is achieved automatically
by updating the control register for all devices together.
For MAX6952s, the devices can be synchronized by
transmitting the serial data for the control register, and
then toggling the CS pin for each device, either togeth-
er or in quick succession. Figure 7 is the multiplex tim-
ing diagram.
Blink Output
The blink output indicates the blink phase, and is high
during the P0 period and low during the P1 period.
Blink phase status can also be read back as the P bit in
the configuration register (Table 13). Typical uses for
this output are:
To provide an interrupt to the processor so that seg-
ment data can be changed synchronous to the
blinking. For example, a clock application may have
colon segments blinking every second between
hours and minute digits, and the minute display is
best changed in step with the colon segments. Also,
if the rising edge of blink is detected, there is half a
blink period to change the P1 digit data. Similarly, if
the falling edge of blink is detected, the user has
half a blink period to change the P0 digit data.
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
x000 x001 x010 x011 x100 x101 x110
x111
RAM00
RAM01
RAM02
RAM03
RAM04
RAM05
RAM06
RAM07
MSB
LSB
RAM08
RAM09
RAM10
RAM11
RAM12
RAM13
RAM14
RAM15
RAM16
RAM17
RAM18
RAM19
RAM20
RAM21
RAM22
RAM23
Table 14. Character Map
MAX6952
4-Wire Interfaced, 2.7V to 5.5V,
4-Digit 5
7 Matrix LED Display Driver
14 ______________________________________________________________________________________
If OSC is driven with an accurate frequency, blink
can be used as a seconds counter or similar.
Scan-Limit Register
The scan-limit register sets how many monocolor digits
are displayed, either two or four. A bicolor digit is con-
nected as two monocolor digits.
The multiplexing scheme drives digits 0 and 1 at the
same time, then digits 2 and 3 at the same time. To
increase the effective brightness of the displays, drive
only two digits instead of four. By doing this, the aver-
age segment current doubles, but also doubles the
number of MAX6952s required to drive a given number
of digits.
Because digit 1 is driven at the same time as digit 0
(and digit 3 is driven at the same time as digit 2), only 1
bit is used to set the scan limit. The bit is clear if one or
two digits are to be driven, and set if three or four digits
are to be driven (Table 20). Change the scan-limit
register only when the MAX6952 is in shutdown mode.
Intensity Registers
Display brightness is controlled digitally by four pulse-
width modulators, one for each display digit. Each digit is
controlled by a nibble of one of the two intensity registers,
Intensity10 and Intensity32. The modulator scales the
average segment current in 16 steps from a maximum of
15/16 down to 1/16 of the peak current. The minimum
interdigit blanking time is, therefore, 1/16 of a cycle. The
maximum duty cycle is 15/16. (Tables 21 and 22).
No-Op Register
A write to the no-op register is ignored.
Selecting External Components R
SET
and
C
SET
to Set Oscillator Frequency and
Segment Current
The RC oscillator uses an external resistor RSET and an
external capacitor C
SET
to set the oscillator frequency,
f
OSC
. The allowed range of f
OSC
is 1MHz to 8MHz.
R
SET
also sets the peak segment current. The recom-
mended values of R
SET
and C
SET
set the oscillator to
4MHz, which makes the blink frequencies 0.5Hz and
1Hz. The recommended value of R
SET
also sets the
peak current to 40mA, which makes the segment cur-
rent adjustable from 2.5mA to 37.5mA in 2.5mA steps:
I
SEG
= K
I
/ R
SET
mA
f
OSC
= K
F
/ (R
SET
C
SET
+ C
STRAY
) MHz
Where:
K
I
= 2144
K
F
= 6000
R
SET
= external resistor in k
C
SET
= external capacitor in pF
C
STRAY
= stray capacitance from OSC pin to GND in
pF, typically 2pF
The recommended value of R
SET
is 53.6k and the
recommended value of C
SET
is 26pF.
ADDRESS CODE
(HEX)
REGISTER
DATA
SPI READ
OR WRITE
FUNCTION
0x85 0x000x7F Read
Read 7-bit user-definable font data entry from current font
address. MSB of the register data is clear. Font address
pointer is incremented after the read.
0x05 0x000x7F Write
Write 7-bit user-definable font data entry to current font
address. Font address pointer is incremented after the
write.
0x05 0x800xFF Write Write font address pointer with the register data.
Table 15. Memory Mapping of User-Defined Font Register 0x05
FONT POINTER ADDRESS ACTION
0x80 to 0xF6
Valid range to set the font address pointer. Pointer autoincrements after a font data read or
write, while pointer address remains in this range.
0xF7 Font address resets to 0x80 after a font data read or write to this pointer address.
0xF8 to 0xFF Invalid range to set the font address pointer. Pointer is set to 0x80 if address.
Table 16. Font Pointer Address Behavior
MAX6952
4-Wire Interfaced, 2.7V to 5.5V,
4-Digit 5
7 Matrix LED Display Driver
______________________________________________________________________________________ 15
REGISTER DATA
FONT
CHARACTER
ADDRESS
CODE (HEX)
REGISTER
DATA (HEX)
D7 D6 D5 D4 D3 D2 D1 D0
RAM00 0x05 0x80 1 0 0 0 0 0 0 0
RAM01 0x05 0x85 1 0 0 0 0 1 0 1
RAM02 0x05 0x8A 1 0 0 0 1 0 1 0
RAM03 0x05 0x8F 1 0 0 0 1 1 1 1
RAM04 0x05 0x94 1 0 0 1 0 1 0 0
RAM05 0x05 0x99 1 0 0 1 1 0 0 1
RAM06 0x05 0x9E 1 0 0 1 1 1 1 0
RAM07 0x05 0xA3 1 0 1 0 0 0 1 1
RAM08 0x05 0xA8 1 0 1 0 1 0 0 0
RAM09 0x05 0xAD 1 0 1 0 1 1 0 1
RAM10 0x05 0xB2 1 0 1 1 0 0 1 0
RAM11 0x05 0xB7 1 0 1 1 0 1 1 1
RAM12 0x05 0xBC 1 0 1 1 1 1 0 0
RAM13 0x05 0xC1 1 1 0 0 0 0 0 1
RAM14 0x05 0xC6 1 1 0 0 0 1 1 0
RAM15 0x05 0xCB 1 1 0 0 1 0 1 1
RAM16 0x05 0xD0 1 1 0 1 0 0 0 0
RAM17 0x05 0xD5 1 1 0 1 0 1 0 1
RAM18 0x05 0xDA 1 1 0 1 1 0 1 0
RAM19 0x05 0xDF 1 1 0 1 1 1 1 1
RAM20 0x05 0xE4 1 1 1 0 0 1 0 0
RAM21 0x05 0xE9 1 1 1 0 1 0 0 1
RAM22 0x05 0xEE 1 1 1 0 1 1 1 0
RAM23 0x05 0xF3 1 1 1 1 0 0 1 1
Table 17. User-Definable Font Pointer Base Address Table
The recommended value of R
SET
is the minimum
allowed value since it sets the display driver to the
maximum allowed segment current. R
SET
can be set to
a higher value to set the segment current to a lower
peak value where desired. The user must also ensure
that the peak current specifications of the LEDs con-
nected to the driver are not exceeded.
The effective value of C
SET
includes not only the actual
external capacitor used, but also the stray capacitance
from OSC to GND. This capacitance is usually in the
1pF to 5pF range, depending on the layout used.
Display-Test Register
The display-test register switches the drivers between
one of two modes: normal and display test. Display-test
mode turns all LEDs on by overriding, but not altering,
all control and digit registers (including the shutdown
register). In display-test mode, eight digits are scanned
and the duty cycle is 7/16 (half power). Table 23 lists
the display-test register format.
Applications Information
Choosing Supply Voltage to Minimize
Power Dissipation
The MAX6952 drives a peak current of 40mA into LEDs
with a 2.4V forward-voltage drop when operated from a
supply voltage of at least 3.0V. The minimum voltage
drop across the internal LED drivers is, therefore (3.0V -
2.4V) = 0.6V. If a higher supply voltage is used, the dri-
ver absorbs a higher voltage, and the drivers power
dissipation increases accordingly. However, if the LEDs
used have a higher forward voltage drop than 2.4V, the
supply voltage must be raised accordingly to ensure
that the driver always has at least 0.6V headroom.

MAX6952EPL+

Mfr. #:
Manufacturer:
Maxim Integrated
Description:
LED Display Drivers MAX6952EPL+
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