1
INDUSTRIAL TEMPERATURE RANGE
IDT5T929
PRECISION CLOCK GENERATOR OC-48 APPLICATIONS
2013 Integrated Device Technology, Inc. DSC 6400/17c
IDT5T929
INDUSTRIAL TEMPERATURE RANGE
PRECISION CLOCK GENERATOR
OC-48 APPLICATIONS
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
FEATURES:
• Input frequency:
- For SONET non-FEC: 19.44MHz, 38.88MHz, 77.76MHz, 155.52MHz,
311.04MHz, or 622.08MHz
- For SONET FEC: 20.83MHz, 41.66MHz, 83.31MHz, 166.63MHz,
333.26MHz, or 666.52MHz
- For 10GE copper: 19.53MHz, 39.06MHz, 78.125MHz, 156.25MHz,
312.5MHz, or 625MHz
- For 10GE optical: 20.14MHz, 40.28MHz, 80.56MHz, 161.13MHz,
322.26MHz, or 644.53MHz
• Output frequency range selection
• 1x, 2x, 4x, 8x, 16x, and 32x outputs on QOUT
• Regenerated input clock on QREG
• Lock indicator
• Power-down mode
• LVPECL or LVDS outputs
• Two modes of output frequency range
- Mode 0: QOUT range 155.5 - 166.6MHz. QREG is a regenerated version
of the input clock.
- Mode 1: QOUT range 622 - 666.5MHz. QREG is a regenerated version
of the input clock frequency.
• Hitless switchover
• Differential LVPECL, LVDS, or single-ended LVTTL input interface
• 2.375 - 3.465V core and I/O
• Available in VFQFPN package
• use Replacement part: 8T49N222B-dddNLGI
DESCRIPTION:
The IDT5T929 generates a high precision FEC (Forward Error Cor-
rection) or non-FEC source clock for SONET/SDH systems as well as a
source clock for Gigabit Ethernet systems. This device also has clock
regeneration capability: it creates a "clean" version of the clock input by
using the internal oscillator to square the input clock's rising and falling
edges and remove jitter. In the event that the main clock input fails, the
device automatically locks to a backup reference clock using a hitless
switchover mechanism.
This device detects loss of valid CLKIN and leaves the VCO of the PLL at
the last valid frequency while an alternate input REFIN is selected. If CLKIN
and REFIN are different frequencies, the multiplication factor will be adjusted to
retain the same output frequency.
The IDT5T929 can act as a translator from a differential LVPECL, LVDS, or
single-ended LVTTL input to LVPECL or LVDS outputs. The IDT5T929-10
has LVDS outputs and the IDT5T929-30 has LVPECL outputs.
The two modes of output frequency range are controlled by the SELmode.
When SELmode is high or low, the Q
OUT is a multiplied version of the input clock
while QREG is a regenerated version of the input clock.
APPLICATIONS:
• Terabit routers
• Gigabit ethernet systems
• SONET / SDH systems
• Digital cross connects
• Optical transceiver modules
PLL
CONTROL
LOGIC
LOCK,
FREQ.
DETECTOR
CLKIN
REFIN
LOCK
DIVN
DIVM
QREG
QOUT
SELMODE
PD
INPUT
MUX
CLKIN
REFIN
QREG
QOUT
FUNCTIONAL BLOCK DIAGRAM
PRODUCT DISCONTINUATION NOTICE - LAST TIME BUY EXPIRES ON OCTOBER 28, 2014
MAY 2013
