ZL50017 Data Sheet
33
Zarlink Semiconductor Inc.
0STIN[n]ENInput Stream Enable Bit
When this bit is high the input stream is enabled. When this bit is low the input
stream is ignored
Note: [n] denotes input stream from 0 - 15.
Bit Name Description
15 - 9 Unused Reserved
In normal functional mode, these bits MUST be set to zero.
8 - 7 STO[n]FA1 - 0
Output Stream[n] Fractional Advancement Bits
6 - 4 STO[n]AD2 - 0 Output Stream[n] Bit Advancement Selection Bits
The binary value of these bits refers to the number of bits that the output stream
is to be advanced relative to FPi. The maximum value is 7. Zero means no
advancement.
3 - 1 Unused Reserved
In normal functional mode, these bits MUST be set to zero
.
0 STO[n]EN Output Stream Enable Bit
When this bit is high the output stream is enabled. When this bit is low the
output stream is set to high impedance
Note: [n] denotes output stream from 0 - 15.
Table 10 - Stream Output Control Register 0 - 15 (SOCR0 - 15) Bits
Bit Name Description
Table 9 - Stream Input Control Register 0 - 15 (SICR0 - 15) Bits (continued)
External Read/Write Address: 0100
H
- 010F
H
Reset Value: 0000
H
1514131211109876543210
0000000STIN[n]
BD2
STIN[n]
BD1
STIN[n]
BD0
STIN[n]
SMP1
STIN[n]
SMP0
000STIN[n]
EN
External Read/Write Address: 0200
H
- 020F
H
Reset Value: 0000
H
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0000
0 0 0 STO[n]
FA1
STO[n]
FA0
STO[n]
AD2
STO[n]
AD1
STO[n]
AD0
0 0 0 STO[n]
EN
STO[n]FA1-0
Advancement
(2.048 Mbps, 4.096 Mbps,
8.192 Mbps streams)
Advancement
(16.384 Mbps streams)
00 0 0
01 1/4 bit 2/4
10 2/4 bit Reserved
11 3/4 bit
