ZL50017 Data Sheet
41
Zarlink Semiconductor Inc.
† Characteristics are over recommended operating conditions unless otherwise stated.
‡ Typical figures are at 25°C, VDD_CORE at 1.8 V and VDD_IO at 3.3 V and are for design aid only: not guaranteed and not subject to produc-
tion testing.
Figure 17 - Intel Non-Multiplexed Bus Timing - Read Access
AC Electrical Characteristics
†
- Intel Non-Multiplexed Bus Mode - Read Access
Characteristics Sym. Min. Typ.
‡
Max. Units Test Conditions
2
1CS de-asserted time t
CSD
15 ns
2RD
setup to CS falling t
RS
10 ns
3WR
setup to CS falling t
WS
10 ns
4 Address setup to CS
falling t
AS
5ns
5RD
hold after CS rising t
RH
0ns
6WR
hold after CS rising t
WH
0ns
7 Address hold after CS
rising t
AH
0ns
8 Data setup to RDY high t
DS
8nsC
L
= 50 pF
9 Data Active to High Impedance t
CSZ
7nsC
L
= 50 pF, R
L
= 1 K
(Note 1)
10 Acknowledgement delay time.
From CS
low to RDY high:
Registers
Memory
t
AKD
175
185
ns
ns
C
L
= 50 pF
C
L
= 50 pF
11 Acknowledgement hold time.
From CS
high to RDY low
t
AKH
412nsC
L
= 50 pF, R
L
= 1 K
(Note 1)
12 RDY drive low to HiZ t
AKZ
8ns
Note 1: High impedance is measured by pulling to the appropriate rail with R
L
, with timing corrected to cancel time taken to
discharge C
L
.
Note 2: A delay of 500 µs to 2 ms (see Section 10.2 on page 25) must be applied before the first microprocessor access is
performed after the RESET
pin is set high.
CS
A0-A13
D0-D15
t
AH
t
WS
WR
t
WH
t
AKD
t
DS
t
AKH
RDY
V
CT
V
CT
V
CT
V
CT
V
CT
VALID ADDRESS
VALID READ DATA
t
CSD
t
AKZ
t
RS
RD
t
RH
V
CT
t
AS
t
CSZ
