T
T
T
S
S
S
2
2
2
Q
Q
Q
S
S
S
U
U
U
2
2
2
3
3
3
0
0
0
0
0
0
3
3
3
-
-
-
4
4
4
S
S
S
200PIN DDR2 800 SO-DIMM
1GB With 128Mx8 CL6
Transcend Information Inc.
IDD Specification parameters Definition
( IDD values are for full operating range of voltage and Temperature)
Parameter Symbol
Max.
Unit
Note
Operating One bank Active-Precharge current; tCK = tCK(IDD), tRC = tRC(IDD),
tRAS = tRASmin(IDD); CKE is HIGH, /CS is HIGH between valid commands;
Address bus inputs are SWITCHING; Data bus inputs are SWITCHING
IDD0 520 mA
Operating One bank Active-read-Precharge current; IOUT = 0mA; BL = 4, CL =
CL(IDD), AL = 0; tCK = tCK(IDD), tRC = tRC (IDD), tRAS = tRASmin(IDD), tRCD =
tRCD(IDD); CKE is HIGH, /CS is HIGH between valid commands; Address bus
inputs are SWITCHING; Data pattern is same as IDD4W
IDD1 600 mA
Precharge power-down current; All banks idle; tCK = tCK(IDD); CKE is LOW;
Other control and address bus inputs are STABLE; Data bus inputs are FLOATING
IDD2P
80 mA
Precharge quiet standby current; All banks idle; tCK = tCK(IDD); CKE is HIGH,
CS\ is HIGH; Other control and address bus inputs are STABLE; Data bus inputs are
FLOATING
IDD2Q
200 mA
Precharge standby current; All banks idle; tCK = tCK(IDD); CKE is HIGH, /CS is
HIGH; Other control and address bus inputs are SWITCHING; Data bus inputs are
SWITCHING
IDD2N
256 mA
Fast PDN Exit MRS(12) = 0
IDD3P-F
224
Active power - down current;
All banks open; tCK
= tCK(IDD); CKE is LOW; Other control and address
bus inputs are STABLE; Data bus inputs are
FLOATING
Slow PDN Exit MRS(12) = 1 IDD3P-S
120
mA
Active standby current; All banks open; tCK = tCK(IDD), tRAS = tRASmax(IDD),
tRP = tRP(IDD); CKE is HIGH, /CS is HIGH between valid commands; Other control
and address bus inputs are SWITCHING; Data bus inputs are SWITCHING
IDD3N
320 mA
Operating burst read current; All banks open, Continuous burst reads, IOUT =
0mA; BL = 4, CL = CL(IDD), AL = 0; tCK = tCK(IDD), tRAS = tRASmax(IDD), tRP =
tRP(IDD); CKE is HIGH, /CS is HIGH between valid commands; Address bus inputs
are SWITCHING; Data pattern is same as IDD4W
IDD4R
1,000
mA
Operating burst write current; All banks open, Continuous burst writes; BL = 4, CL
= CL(IDD), AL = 0; tCK = tCK(IDD), tRAS = tRASmax(IDD), tRP = tRP(IDD); CKE is
HIGH, CS\ is HIGH between valid commands; Address bus inputs are SWITCHING;
Data bus inputs are SWITCHING
IDD4W
760 mA
Burst Auto refresh current;
tCK = tCK(IDD); Refresh command at every tRFC(IDD)
interval; CKE is HIGH, /CS is HIGH between valid commands; Other control and
address bus inputs are SWITCHING; Data bus inputs are SWITCHING
IDD5B
816 mA
Self refresh current; CK and /CK at 0V; CKE 0.2V; Other control and address
bus inputs are FLOATING; Data bus inputs are FLOATING
IDD6 80 mA
Operating bank interleave read current; All bank interleaving reads, IOUT = 0mA;
BL = 4, CL = CL(IDD), AL = tRCD(IDD)-
1*tCK(IDD); tCK =tCK(IDD), tRC = tRC(IDD),
tRRD = tRRD(IDD), tRCD = 1*tCK(IDD); CKE is HIGH, CS\ is HIGH between valid
commands; Address bus inputs are STABLE during Deselects; Data pattern is same
as IDD4R; Refer to the following page for detailed timing conditions
IDD7 1,600
mA
Note: 1. Module I
DD
was calculated on the basis of component I
DD
and can be differently measured according to DQ
loading capacitor.
