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78Q2123SR/F

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P38
78Q2123/78Q2133 Data Sheet DS_21x3_001
16 Rev. 1.6
3.2 MR1: Status Register
Bits 1.15 through 1.11 reflect the ability of the 78Q2123/78Q2133. They do not reflect any ability changes
made via the MII Management Interface to bits 0.13 (SPEEDSL) , 0.12 (ANEGEN) and 0.8 (DUPLEX) in
the Control Register.
Bit Symbol Type Default Description
1.15 100T4 R 0 100BASE-T4 Ability: Reads ‘0’ to indicate the
78Q2123/78Q2133 do not support 100Base-T4 mode.
1.14 100X_F R 1 100BASE-TX Full Duplex Ability:
0 : Not able
1 : Able
1.13 100X_H R 1 100BASE-TX Half Duplex Ability:
0 : Not able
1 : Able
1.12 10T_F R 1 10BASE-T Full Duplex Ability:
0 : Not able
1 : Able
1.11 10T_H R 1 10BASE-T Half Duplex Ability:
0 : Not able
1 : Able
1.10 100T2_F R 0 100BASE-T2 Full Duplex Ability: Reads ‘0’ to indicate the
78Q2123/78Q2133 do not support 100Base-T2 full duplex
mode.
1.9 100T2_H R 0 100BASE-T2 Half Duplex Ability: Reads ‘0’ to indicate the
78Q2123/78Q2133 do not support 100Base-T2 full duplex
mode.
1.8 EXTS R 0 Extended Status Information Availability: Reads ‘0’ to indicate
the 78Q2123/78Q2133 do not support Extended Status
information on MR15.
1.7 RSVD R 0 Reserved
1.6 MFPS R 0 Management Frame Preamble Suppression Support: A “0”
indicates that the 78Q2123/78Q2133 can read management
frames with a preamble.
1.5 ANEGC R 0 Auto-Negotiation Complete: A logic one indicates that the
Auto-Negotiation process has been completed, and that the
contents of registers MR4,5,6 are valid.
1.4 RFAULT RC 0 Remote Fault: A logic one indicates that a remote fault
condition has been detected and it remains set until it is
cleared. This bit can only be cleared by reading this register
(MR1) via the management interface.
1.3 ANEGA R (1) Auto-Negotiation Ability: When set, this bit indicates the
device’s ability to perform Auto-Negotiation. The value of this
bit is determined by the
ANEGEN
bit (MR0.12).
1.2 LINK R 0 Link Status: A logic one indicates that a valid link has been
established. If the link status should transition from an OK
status to a NOT-OK status, this bit will become cleared and
remains cleared until it is read.
1.1 JAB RC 0 Jabber Detect: In 10Base-T mode, this bit is set during a
jabber event. After a jabber event, the bit remains set until
DS_21x3_001 78Q2123/78Q2133 Data Sheet
Rev. 1.6 17
cleared by a read operation.
1.0 EXTD R 1 Extended Capability: Reads ’1’ to indicate the
78Q2123/78Q2133 provide an extended register set (MR2
and beyond).
3.3 MR2: PHY Identifier Register 1
Bit Symbol Type Value Description
2.15:0 OUI [23:6] R 000Eh Organizationally Unique Identifier: This value is 00-C0-39 for
Teridian Semiconductor Corporation. This register contains the
first 16-bits of the identifier.
3.4 MR3: PHY Identifier Register 2
Bit Symbol Type Value Description
3.15:10 OUI [5:0] R 1Ch Organizationally Unique Identifier: Remaining 6 bits of the
OUI.
3.9:4 MN R 23h Model Number: The last 2 digits of the model number
78Q2123 are encoded into the 6 bits for both 78Q2123 and
78Q2133.
3.3:0 RN R 07h
Revision Number: The value ‘0111’ corresponds to the
seventh revision of the silicon.
3.5 MR4: Auto-Negotiation Advertisement Register
Bit Symbol Type Default Description
4.15 NP R 0 Next Page: Not supported. Reads logic zero.
4.14 RSVD R 0 Reserved
4.13 RF R/W 0 Remote Fault: Setting this bit to ‘1’ allows the device to
indicate to the link partner a Remote Fault Condition.
4.12 A7 R 0 Reserved.
4.11 A6 R/W 0 Asymmetric PAUSE Support Indication for Full Duplex Links.
Default is 0 indicating not supported. If the MAC supports
Asymmetric PAUSE, this bit can be written as 1. Writing to this
register has no effect until auto-negotiation is re-initiated.
4.10 A5 R 0 PAUSE Support Indication for Full Duplex Links. Default is 0
indicating not supported. If the MAC supports PAUSE, this bit
can be written as 1. Writing to this register has no effect until
auto-negotiation is re-initiated
4.9 A4 R 0 100BASE-T4: The 78Q2123/78Q2133 do not support
100BASE-T4 operation.
4.8 A3 R/W (1) 100BASE-TX Full Duplex: If the MR1.14 bit is ‘1’, this bit will
be set to ‘1’ upon reset and will be writeable. Otherwise, this
bit cannot be set to ‘1’ by the management.
4.7 A2 R/W (1) 100BASE-TX: If the MR1.13 bit is ‘1’, this bit will be set to ‘1’
upon reset and will be writeable. Otherwise, this bit cannot be
set to ‘1’ by the management.
4.6 A1 R/W (1) 10BASE-T Full Duplex: If the MR1.12 bit is ‘1’, this bit will be
set to ‘1’ upon reset and will be writeable. Otherwise, this bit
cannot be set to ‘1’ by the management.
78Q2123/78Q2133 Data Sheet DS_21x3_001
18 Rev. 1.6
4.5 A0 R/W (1) 10BASE-T: If the MR1.11 bit is ‘1’, this bit will be set to ‘1’
upon reset and will be writeable. Otherwise, this bit cannot be
set to ‘1’ by the management.
4.4:0 S4:0 R 01h Selector Field: Hard coded with the value of ‘00001’ for IEEE
802.3.
Note: Technology Ability Field: MR4.12:5 are the Technology Ability Field bits (A7:0). The default value
of this field is dependent upon the MR1.15:11 register bits. This field can be overwritten by management
to auto-negotiate to an alternate common technology. Writing to this register has no effect until
auto-negotiation is re-initiated.
3.6 MR5: Auto-Negotiation Link Partner Ability Register
Bit Symbol Type Default Description
5.15 NP R 0 Next Page: When ‘1’ is read, it indicates the link partner
wishes to engage in Next Page exchange.
5.14 ACK R 0
Acknowledge: When ‘1’ is read, it indicates the link partner has
successfully received at least 3 consecutive and consistent
FLP bursts.
5.13 RF R 0 Remote Fault: When ‘1’ is read, it indicates the link partner has
a fault.
5.12:5 A7:0 R 0 Technology Ability Field: This field contains the technology
ability of the link partner. The bit definition is the same as
MR4.12:5.
5.4:0 S4:0 R 00h Selector Field: This field contains the type of message sent by
the link partner. For an IEEE 802.3 compliant link partner, this
field should be ‘00001’.
3.7 MR6: Auto-Negotiation Expansion Register
Bit Symbol Type Default Description
6.15:5 RSVD R 0 Reserved
6.4 PDF RC 0 Parallel Detection Fault: When ‘1’ is read, it indicates that
more than one technology has been detected during link up.
This bit is cleared when read.
6.3 LPNPA R 0
Link Partner Next Page Able: When ‘1’ is read, it indicates the
link partner supports the Next Page function.
6.2 NPA R 0
Next Page Able: Reads ‘0’ since the 78Q2123/78Q2133 do not
support Next Page function.
6.1 PRX RC 0 Page Received: Reads ‘1’ when a new link code word has
been received into the Auto-Negotiation Link Partner Ability
Register. This bit is cleared upon read.
6.0 LPANEGA R 0 Link Partner Auto-Negotiation Able: When ‘1’ is read, it
indicates the link partner is able to participate in the Auto-
Negotiation function.
3.8 MR16: Vendor Specific Register
Bit Symbol Type Default Description
16.15 RPTR R/W (0) Repeater Mode: When set, the 78Q2123/78Q2133 are put
into Repeater mode of operation. In this mode, full duplex is
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P38

78Q2123SR/F

Mfr. #:
Buy 78Q2123SR/F
Manufacturer:
Maxim Integrated
Description:
Ethernet ICs 10/100 Base Tx Transcvr w/MDIX
Lifecycle:
New from this manufacturer.
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