10
FN9182.2
April 4, 2006
The charging time of the ramp capacitor is
For optimum performance, the maximum value of the
capacitor should be limited to 10nF. The maximum DC
current through the resistor should be limited to 2mA
maximum. For example, if the oscillator frequency is
400kHz, the minimum input voltage is 300V, and a 4.7nF
ramp capacitor is selected, the value of the resistor can be
determined by rearranging Equation 7.
where t is equal to the oscillator period minus the deadtime.
If the deadtime is short relative to the oscillator period, it can
be ignored for this calculation.
If feed forward operation is not desired, the RC network may
be connected to VREF rather than the input voltage.
Alternatively, a resistor divider from CTBUF may be used as
the sawtooth signal. Regardless, a sawtooth waveform must
be generated on RAMP as it is required for proper PWM
operation.
Slope Compensation
Peak current-mode control requires slope compensation to
improve noise immunity, particularly at lighter loads, and to
prevent current loop instability, particularly for duty cycles
greater than 50%. Slope compensation may be
accomplished by summing an external ramp with the current
feedback signal or by subtracting the external ramp from the
voltage feedback error signal. Adding the external ramp to
the current feedback signal is the more popular method.
From the small signal current-mode model [1] it can be
shown that the naturally-sampled modulator gain, Fm,
without slope compensation, is
where Sn is the slope of the sawtooth signal and Tsw is the
duration of the half-cycle. When an external ramp is added,
the modulator gain becomes
where Se is slope of the external ramp and
The criteria for determining the correct amount of external
ramp can be determined by appropriately setting the
damping factor of the double-pole located at half the
oscillator frequency. The double-pole will be critically
damped if the Q-factor is set to 1, and over-damped for
Q > 1, and under-damped for Q < 1. An under-damped
condition can result in current loop instability.
where D is the percent of on time during a half cycle. Setting
Q = 1 and solving for Se yields:
Since S
n
and S
e
are the on time slopes of the current ramp
and the external ramp, respectively, they can be multiplied
by Ton to obtain the voltage change that occurs during Ton.
where Vn is the change in the current feedback signal during
the on time and Ve is the voltage that must be added by the
external ramp.
Vn can be solved for in terms of input voltage, current
transducer components, and output inductance yielding:
where R
CS
is the current sense burden resistor, N
CT
is the
current transformer turns ratio, L
O
is the output inductance,
V
O
is the output voltage, and Ns and Np are the secondary
and primary turns, respectively.
The inductor current, when reflected through the isolation
transformer and the current sense transformer to obtain the
current feedback signal at the sense resistor yields:
where V
CS
is the voltage across the current sense resistor
and I
O
is the output current at current limit.
Since the peak current limit threshold is 1.00V, the total
current feedback signal plus the external ramp voltage must
sum to this value.
Substituting Equations 15 and 16 into Equation 17 and
solving for R
CS
yields
tR3C71
V
RAMP PEAK()
V
IN MIN()
----------------------------------------



ln⋅⋅= S
(EQ. 7)
R3
t
C7 1
V
RAMP PEAK()
V
IN MIN)()
----------------------------------------



ln
-------------------------------------------------------------------------
2.5 10
6
4.7 10
9
1
1
300
----------


ln⋅⋅
------------------------------------------------------------==
159= k
(EQ. 8)
Fm
1
SnTsw
--------------------
=
(EQ. 9)
Fm
1
Sn Se+()Tsw
---------------------------------------
1
m
c
SnTsw
----------------------------
==
(EQ. 10)
m
c
1
Se
Sn
-------
+=
(EQ. 11)
Q
1
π m
c
1D()0.5()
-------------------------------------------------=
(EQ. 12)
S
e
S
n
1
π
--- 0.5+


1
1D
-------------
1


=
(EQ. 13)
V
e
V
n
1
π
--- 0.5+


1
1D
-------------
1


=
(EQ. 14)
V
e
T
SW
V
O
R
CS
N
CT
L
O
------------------------------------------
N
S
N
P
--------
1
π
--- D0.5+


= V
(EQ. 15)
V
CS
N
S
R
CS
N
P
N
CT
------------------------
I
O
DT
SW
2L
O
---------------------
V
IN
N
S
N
P
--------
V
O



+



= V
(EQ. 16)
V
e
V
CS
+ 1=
(EQ. 17)
R
CS
N
P
N
CT
N
S
------------------------
1
I
O
V
O
L
O
--------
T
SW
1
π
---
D
2
----
+


+
------------------------------------------------------
=
(EQ. 18)
ISL6753
11
FN9182.2
April 4, 2006
For simplicity, idealized components have been used for this
discussion, but the effect of magnetizing inductance must be
considered when determining the amount of external ramp
to add. Magnetizing inductance provides a degree of slope
compensation to the current feedback signal and reduces
the amount of external ramp required. The magnetizing
inductance adds primary current in excess of what is
reflected from the inductor current in the secondary.
where V
IN
is the input voltage that corresponds to the duty
cycle D and Lm is the primary magnetizing inductance. The
effect of the magnetizing current at the current sense
resistor, R
CS
, is
If V
CS
is greater than or equal to Ve, then no additional
slope compensation is needed and R
CS
becomes
If V
CS
is less than Ve, then Equation 18 is still valid for the
value of R
CS
, but the amount of slope compensation added
by the external ramp must be reduced by V
CS
.
Adding slope compensation is accomplished in the ISL6753
using the CTBUF signal. CTBUF is an amplified
representation of the sawtooth signal that appears on the CT
pin. It is offset from ground by 0.4V and is 2x the peak-to-
peak amplitude of CT (0.4 - 4.4V). A typical application sums
this signal with the current sense feedback and applies the
result to the CS pin as shown in Figure 7.
Assuming the designer has selected values for the RC filter
placed on the CS pin, the value of R9 required to add the
appropriate external ramp can be found by superposition.
Rearranging to solve for R9 yields
The value of R
CS
determined in Equation 18 must be
rescaled so that the current sense signal presented at the
CS pin is that predicted by Equation 16. The divider created
by R6 and R9 makes this necessary.
Example:
V
IN
= 280V
V
O
= 12V
L
O
= 2.0µH
Np/Ns = 20
Lm = 2mH
I
O
= 55A
Oscillator Frequency, Fsw = 400kHz
Duty Cycle, D = 85.7%
N
CT
= 50
R6 = 499
Solve for the current sense resistor, R
CS
, using Equation 18.
R
CS
= 15.1.
Determine the amount of voltage, Ve, that must be added to
the current feedback signal using Equation 15.
Ve = 153mV
Next, determine the effect of the magnetizing current from
Equation 20.
V
CS
= 91mV
Using Equation 23, solve for the summing resistor, R9, from
CTBUF to CS.
R9 = 30.1k
Determine the new value of R
CS
, R’
CS
, using Equation 24.
R’
CS
= 15.4
The above discussion determines the minimum external
ramp that is required. Additional slope compensation may be
considered for design margin.
I
P
V
IN
DT
SW
L
m
-------------------------------= A
(EQ. 19)
V
CS
I
P
R
CS
N
CT
--------------------------= V
(EQ. 20)
R
CS
N
CT
N
S
N
P
--------
I
O
DT
SW
2L
O
-----------------
V
IN
N
S
N
P
--------
V
O



+



V
IN
DT
SW
L
m
-------------------------------
+
--------------------------------------------------------------------------------------------------------------------------------------
=
(EQ. 21)
FIGURE 7. ADDING SLOPE COMPENSATION
R6
C4
R9
CTBUF
CS
1
2
4
3
5
6
7
8
R
CS
ISL6753
V
e
V
CS
DV
CTBUF
0.4()0.4+()R6
R6 R9+
-------------------------------------------------------------------------------= V
(EQ. 22)
R9
DV
CTBUF
0.4()V
e
V
CS
0.4++()R6
V
e
V
CS
-------------------------------------------------------------------------------------------------------------------
=
(EQ. 23)
R
CS
R6 R9+
R9
----------------------
R
CS
=
(EQ. 24)
ISL6753
12
FN9182.2
April 4, 2006
If the application requires deadtime less than about 500ns,
the CTBUF signal may not perform adequately for slope
compensation. CTBUF lags the CT sawtooth waveform by
300-400ns. This behavior results in a non-zero value of
CTBUF when the next half-cycle begins when the deadtime
is short.
Under these situations, slope compensation may be added
by externally buffering the CT signal as shown below.
Using CT to provide slope compensation instead of CTBUF
requires the same calculations, except that Equations 21
and 22 require modification. Equation 21 becomes:
and Equation 22 becomes:
The buffer transistor used to create the external ramp from
CT should have a sufficiently high gain so as to minimize the
required base current. Whatever base current is required
reduces the charging current into CT and will reduce the
oscillator frequency.
ZVS Full-Bridge Operation
The ISL6753 is a full-bridge zero-voltage switching (ZVS)
PWM controller that behaves much like a traditional hard-
switched topology controller. Rather than drive the diagonal
bridge switches simultaneously, the upper switches (OUTUL,
OUTUR) are driven at a fixed 50% duty cycle and the lower
switches (OUTLL, OUTLR) are pulse width modulated on
the trailing edge.
To understand how the ZVS method operates one must
include the parasitic elements of the circuit and examine a
full switching cycle.
In Figure 10, the power semiconductor switches have been
replaced by ideal switch elements with parallel diodes and
capacitance, the output rectifiers are ideal, and the
transformer leakage inductance has been included as a
discrete element. The parasitic capacitance has been
lumped together as switch capacitance, but represents all
parasitic capacitance in the circuit including winding
capacitance. Each switch is designated by its position, upper
left (UL), upper right (UR), lower left (LL), and lower right
(LR). The beginning of the cycle, shown in Figure 11, is
arbitrarily set as having switches UL and LR on and UR and
LL off. The direction of the primary and secondary currents
are indicated by I
P
and I
S
, respectively.
FIGURE 8. ADDING SLOPE COMPENSATION USING CT
R6
C4
R9
R
CS
CT
CT
CS
1
2
4
3
5
6
7
89
10
11
12
13
14
15
16
ISL6753
VREF
V
e
V
CS
2D R6
R6 R9+
----------------------= V
(EQ. 25
)
R9
2D V
e
V
CS
+()R6
V
e
V
CS
-------------------------------------------------------------=
(EQ. 26)
FIGURE 9. BRIDGE DRIVE SIGNAL TIMING
CT
DEADTIME
OUTLL
OUTLR
OUTUR
OUTUL
RESDEL
WINDOW
RESONANT
DELAY
PWM
PWM
PWM
PWM
FIGURE 10. IDEALIZED FULL-BRIDGE
VIN+
VIN-
UL
LL
UR
LR
VOUT+
RTN
L
L
D2
D1
ISL6753

ISL6753AAZA-T

Mfr. #:
Manufacturer:
Renesas / Intersil
Description:
Switching Controllers ZVS FL BRDG CNTRLR 16LD QSOP W/ANNEAL
Lifecycle:
New from this manufacturer.
Delivery:
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