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MAX3634ETM+

P1-P3P4-P6P7-P8
General Description
The MAX3634 burst-mode clock phase aligner (CPA) is
designed specifically for 622Mbps or 1244Mbps GPON
(ITU G.984) optical line terminal (OLT) receiver applica-
tions. The MAX3634 provides clock and clock-aligned
resynchronized upstream data through differential
LVPECL outputs. Using the OLT system clock as a ref-
erence, the MAX3634 aligns to the input data and
acquires within the first 13 bits of the burst. The CPA
operates with received data that is frequency locked to
the OLT reference. The acquisition time, bit-error ratio,
and jitter tolerance all support GPON PMD specifica-
tions. LVPECL high-speed clock and data outputs pro-
vide compatibility with FPGAs at 622Mbps and with the
MAX3885 deserializer at 1244Mbps.
The MAX3634 is available in a low-profile, 7mm x 7mm,
48-lead TQFN package. The MAX3634 operates from a
single +3.3V supply, over the -40°C to +85°C tempera-
ture range.
Applications
622Mbps GPON OLT Receivers
1244Mbps GPON OLT Receivers
Features
♦ DC-Coupled Clock Phase Aligner for Burst-Mode
GPON Applications
♦ 13-Bit Burst Acquisition Time
♦ 0.85UI High-Frequency Jitter Tolerance
♦ Continuous Clock Output
♦ Byte Rate (1/8th Data Rate) Reference Clock Input
♦ Lock Detect Output
♦ LVPECL Serial Data Input and Output
♦ LVPECL Reset Input
MAX3634
622Mbps/1244Mbps Burst-Mode Clock
Phase Aligner for GPON OLT Applications
________________________________________________________________ Maxim Integrated Products 1
Ordering Information
19-3818; Rev 0; 9/05
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
EVALUATION KIT
AVAILABLE
PART
TEMP RANGE
PIN-
PACKAGE
PKG
CODE
MAX3634ETM
-40°C to +85°C
48 TQFN
(7mm x 7mm)
T4877-6
MAX3634
MAX3738
BURST-MODE
TIA/LA
MAX3656
BURST-MODE
LASER DRIVER
MAX3864
MAX3748A
TIA/LA
MAX3872
SONET
CDR
MAX3892
DATA
SERIALIZER
DATA
CLOCK
OLT CLOCK
DATA
BURST RESET
RATESEL
DIVIDE BY 16
DIVIDE BY 8
CONTINUOUS
LASER DRIVER
GPON OPTICAL LINE TERMINATION GPON OPTICAL NETWORK TERMINATION
DATA
DATA
BURST ENABLE
CLOCK
CLOCK
4
UPSTREAM
1244Mbps
DOWNSTREAM
2488Mbps
BURST-MODE
CLOCK PHASE
ALIGNER
Typical Application Circuit
Pin Configuration appears at end of data sheet.
MAX3634
622Mbps/1244Mbps Burst-Mode Clock
Phase Aligner for GPON OLT Applications
2 _______________________________________________________________________________________
ABSOLUTE MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS
(V
CC
= +3.0V to +3.6V, T
A
= -40°C to +85°C. Typical values are at V
CC
= +3.3V, T
A
= +25°C, unless otherwise noted.)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
V
CC
, V
CC
I, V
CC
O, V
CC
V ........................................-0.5V to +4.0V
SDI±, RST
±, REFCLK±,
RATESEL, FILT, TEST.............................-0.5V to (V
CC
+ 0.5V)
LVPECL Output Current (SDO±, SCLK±, LOCK±).............50mA
Continuous Power Dissipation (T
A
= +85°C)
48-Lead TQFN package
(derate 27.8mW/°C above +85°C).............................1800mW
Storage Temperature Range .............................-55°C to +150°C
Operating Ambient Temperature Range .............-40°C to +85°C
Lead Temperature (soldering, 10s) .................................+400°C
PARAMETER
SYMBOL
CONDITIONS MIN TYP
MAX
UNITS
Supply Current I
CC
Not including LVPECL output current 315 390 mA
RATESEL = low
1244.16
Data Rate
RATESEL = high
622.08
Mbps
RATESEL = low
155.52
Reference Clock Input Frequency
RATESEL = high
77.76
MHz
SDI, RST, REFCLK Differential
Input
V
IN
200
1600
mV
P-P
SDI±, RST±, REFCLK± Input
Current
-180
+180
µA
Rate = 1244Mbps 200
RST Input Rise/Fall Times t
r
, t
f
Rate = 622Mbps 200
ps
SDI±, RST±, REFCLK± Common-
Mode Input
V
CC
- 1.49
V
CC
- V
IN
/4
V
T
A
= 0°C to +85°C (Note 1)
V
CC
- 1.81
V
CC
- 1.62
SDO±, SCLK±, LOCK± Output
Voltage Low
V
OL
T
A
= -40°C to 0°C (Note 1)
V
CC
- 1.83
V
CC
- 1.555
V
T
A
= 0°C to +85°C (Note 1)
V
CC
- 1.025
V
CC
- 0.88
SDO±, SCLK±, LOCK± Output
Voltage High
V
OH
T
A
= -40°C to 0°C (Note 1)
V
CC
- 1.085
V
CC
- 0.88
V
622Mbps (Notes 2, 5, 6) 0.73 0.83
Jitter Tolerance
1244Mbps (Notes 2, 5, 6) 0.73 0.81
UI
P-P
Acquisition Time (Notes 2, 3) 13 Bits
Bit-Error Ratio After acquisition (Notes 2, 4) 10
-10
SDO±, LOCK± Transition Time t
r
, t
f
20% to 80% (Note 1) 265 ps
SCLK± Transition Time t
r
, t
f
20% to 80% (Note 1) 200 ps
MAX3634
622Mbps/1244Mbps Burst-Mode Clock
Phase Aligner for GPON OLT Applications
_______________________________________________________________________________________ 3
ELECTRICAL CHARACTERISTICS (continued)
(V
CC
= +3.0V to +3.6V, T
A
= -40°C to +85°C. Typical values are at V
CC
= +3.3V, T
A
= +25°C, unless otherwise noted.)
PARAMETER
CONDITIONS MIN TYP
MAX
UNITS
622Mbps (Notes 1, 2) 500
Serial Data Output Clock-to-Q
Delay (Figure 1)
t
CLK-Q
1244Mbps (Notes 1, 2) 250
ps
622Mbps (Notes 1, 2) 500
Serial Data Output Q-to-Clock
Delay (Figure 1)
t
Q-CLK
1244Mbps (Notes 1, 2) 250
ps
RATESEL Input High V
IH
2V
RATESEL Input Low V
IL
0.8 V
RATESEL Input Current V
IN
= 0V or V
CC
-100
+100
µA
Note 1: PECL output must have external termination of 50Ω to V
CC
- 2V (Thevenin equivalent).
Note 2: AC parameters are guaranteed by design and characterization.
Note 3: From start of PON burst, 101010101010 preamble sequence.
Note 4: BER, acquisition time requirements are met with 100mV
P-P
sinusoidal noise on V
CC
, 0 < f
NOISE
≤ 10MHz.
Note 5: Measured with 20ps
RMS
input random jitter (1.244Mbps), 30ps
RMS
(622Mbps)
Note 6: Jitter tolerance refers to the variation in phase between REFCLK and SDI after acquisition.
Typical Operating Characteristics
(V
CC
= +3.3V and T
A
= +25°C, unless otherwise noted)
1.244Gbps
INPUT AND OUTPUT EYE DIAGRAMS
MAX3634 toc01
200ps/div
SDI
SDO
622Mbps
INPUT AND OUTPUT EYE DIAGRAMS
MAX3634 toc02
400ps/div
SDI
SDO
BURST CAPTURE AT 1.244Gbps
MAX3634 toc03
1ns/div
RST
SDI
SDO
LOCK
(SCLK+) - (SCLK-)
(SDO+) - (SDO-)
t
CLK-Q
t
Q-CLK
Figure 1. Definition of Clock-to-Q and Q-to-Clock Delay
P1-P3P4-P6P7-P8

MAX3634ETM+

Mfr. #:
Buy MAX3634ETM+
Manufacturer:
Maxim Integrated
Description:
Timers & Support Products 622/1244Mbps Burst-M Clock Phase Aligner
Lifecycle:
New from this manufacturer.
Delivery:
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