MAX3634ETM+ Datasheet MAX3634ETM+, MAX3634EVKIT, MAX3634ETM+T | P4-P6

MAX3634

622Mbps/1244Mbps Burst-Mode Clock

Phase Aligner for GPON OLT Applications

4 _______________________________________________________________________________________

PIN NAME FUNCTION

1, 2, 12, 25, 36, 37, 48

GND Supply Ground

3, 6, 7, 10 V

I +3.3V Supply for Input Buffers

4 SDI+ Positive Serial Data Input, LVPECL

5 SDI- Negative Serial Data Input, LVPECL

8 RST+ Positive Reset Input, LVPECL. Reset (= RST+ - RST-) is falling edge triggered.

9 RST- Negative Reset Input, LVPECL

11, 38, 39, 44, 47 V

+3.3V Supply for Digital Circuitry

13–20, 22, 23 TEST Production Test Pins, Reserved. Leave open for normal operation.

21, 24, 26, 29, 32, 35

O +3.3V Supply for Output Buffers

27 LOCK- Negative Lock Status Output, LVPECL

28 LOCK+

Positive Lock Status Output, LVPECL. Lock (= (LOCK+) - (LOCK-)) high indicates that the

MAX3634 has acquired the correct phase.

30 SDO- Negative Serial Data Output, LVPECL

31 SDO+ Positive Serial Data Output, LVPECL

33 SCLK- Negative Serial Clock Output, LVPECL

34 SCLK+ Positive Serial Clock Output, LVPECL

40 RATESEL Rate Select Input, TTL. High selects 622.08Mbps operation.

41, 43 V

V +3.3V Supply for VCO

42 FILT PLL Filter Capacitor. Connect a 0.1µF X7R capacitor from pin 42 to V

45 REFCLK- Negative Reference Clock Input, LVPECL (1/8th data rate)

REFCLK+

Positive Reference Clock Input, LVPECL

Exposed Pad

The exposed pad must be connected to the ground plane for proper thermal performance.

Pin Description

Typical Operating Characteristics (continued)

= +3.3V and T

= +25°C, unless otherwise noted)

JITTER TOLERANCE vs. SDI-TO-REFCLK

PHASE (1.244Gbps)

MAX3634 toc04

SDI-TO-REFCLK PHASE (ps)

JITTER TOLERANCE (UI

P-P

)

600400200

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1.0

0 800

LIMITED BY TEST EQUIPMENT

JITTER TOLERANCE vs. SDI-TO-REFCLK

PHASE (622Mbps)

MAX3634 toc05

SDI-TO-REFCLK PHASE (ps)

JITTER TOLERANCE (UI

P-P

)

600400200

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1.0

0800

LIMITED BY TEST EQUIPMENT

SUPPLY CURRENT

vs. TEMPERATURE

MAX3634 toc06

AMBIENT TEMPERATURE (

SUPPLY CURRENT (mA)

500

220

240

260

280

300

320

340

200

-50 100

EXCLUDES PECL OUTPUT CURRENT

General Description

Theory of Operation

The MAX3634 CPA provides serial clock and data out-

puts for GPON upstream bursts.

The burst-mode CPA operates on the principle that the

recovered clock from the ONT CDR is used at each

ONT to clock upstream data bursts out of the ONT con-

troller. The burst-mode CPA has logic that determines

the correct phase relationship between the upstream

data and the OLT reference clock at the beginning of

each ONT’s burst, and resamples the upstream data at

each bit using that clock.

The burst-mode CPA contains a phase-locked loop

(PLL) that synchronizes its oscillator to the reference

clock input. This oscillator drives a phase splitter, which

generates eight evenly spaced phases of the serial

clock, which are used to sample the input data at 1/8th

bit intervals in eight flip-flops. Combinatorial and

sequential logic measures the preamble, and based on

the phase of the preamble, determines which one of

the eight clock phases is at the center of the input data

bits. The data from the flip-flop associated with this

phase is then steered through a multiplexer to the CPA

output, which requires four or five additional clock peri-

ods until valid data is output. The CPA serial output

clock is continuous, without any phase jumps or dis-

continuities from burst to burst.

The burst-mode CPA requires a preamble sequence of

1010101010101 (13 bits) for correct phase alignment.

Typically, output begins after the 12th bit, although for

certain data/phase relationships, 13 bits are required.

An LVPECL-compatible lock status output is provided,

which indicates when the correct phase has been

acquired and valid serial output data is available. This

output remains low until reset by the burst reset input

(RST). The output data is disabled (held low) during the

period between reset and lock.

Reference Clock Input

The MAX3634 includes a PLL, which multiplies the ref-

erence clock by eight for use in the retiming circuitry.

For correct operation, the REFCLK input must be con-

nected to the OLT byte-rate reference clock, which

must be equal to 1/8th the serial data rate, and must

have a 40% to 60% duty cycle. This must be the same

clock source used to time the downstream data, and

the upstream data must be frequency locked to this

source.

The RATESEL input is used to configure 622Mbps or

1244Mbps operation; when RATESEL is high, the

MAX3634 operates at 622Mbps.

MAX3634

622Mbps/1244Mbps Burst-Mode Clock

Phase Aligner for GPON OLT Applications

_______________________________________________________________________________________ 5

MAX3634

LVPECL

REFCLK+

REFCLK-

LVPECL

SDI+

SDI-

TTL

RATESEL

622Mbps/1244Mbps

PLL/PHASE SPLITTER

MUX

SYNCHRONIZER

PHASE-ACQUISITION LOGIC

RST+

RST-

SDO+

SDO-

LVPECL

SCLK+

SCLK-

LVPECL

LOCK+

LOCK-

BURST-MODE CPA

Figure 2. Functional Block Diagram

MAX3634

Input Stage

The LVPECL serial data input, SDI±, and burst-mode

reset input, RST±, provide 200mV

P-P

sensitivity. The

RST± input rise and fall times (20% to 80%) must not

exceed 200ps. LVPECL inputs must be DC-coupled with

external termination for correct operation with burst data

(see Maxim Application Note HFAN 1.0 for termination

configuration).

Lock Detect

After the first 12 or 13 bits of the preamble, plus 4 or 5

bits of synchronizer delay, LOCK asserts to indicate the

beginning of valid data output.

Applications Information

GPON Burst-Mode Timing

Internally, the MAX3634 requires five internal clock

cycles (8x REFCLK) to initialize itself after receiving the

rest (BRST) signal. It then uses the next 8 bits of pream-

ble (10101010) to measure the phase relationship

between the reference clock and upstream data (after

the internal logic has been reset), and 3 to 5 bits later

begins outputting data. The time interval from BRST to

the end of the preamble must be no less than 18 bits

long. If the 8 bits of preamble that it uses to measure

phase have been excessive pulse-width distortion, the

phase measurement is in error.

The active edge of the reset input (BRST) must arrive at

the MAX3634 after the TIA has finished its level recovery,

but no sooner than 18 bits prior to the end of the (repeat-

ing 10 pattern) preamble, in order to provide adequate

time for the MAX3634 to initialize, measure the phase,

and load the output pipelines. This timing is shown in

Figure 3.

622Mbps/1244Mbps Burst-Mode Clock

Phase Aligner for GPON OLT Applications

6 _______________________________________________________________________________________

DATA INPUT

TO MAX3634

RESET

DSR

: BURST-TO-BURST SEPARATION TIME

: TIA/LA LEVEL RECOVERY TIME

: CPA RESET AND ACQUISITION TIME, ≥ 19 BITS

DSR

DATA VALID GUARD TIME TIA/LA ACQUISITION CPA RESET

(5 BITS)

CPA ACQUISITION

(12 OR 13 BITS)

OUTPUT DATA

VALID

Figure 3. Clock Phase Aligner Operation Timing Diagram

P1-P3 P4-P6 P7-P8

MAX3634ETM+

Mfr. #:

Buy MAX3634ETM+

Manufacturer:

Maxim Integrated

Description:

Timers & Support Products 622/1244Mbps Burst-M Clock Phase Aligner

Lifecycle:

New from this manufacturer.

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MAX3634ETM+

MAX3634ETM+

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