TJA1042 All information provided in this document is subject to legal disclaimers. © NXP N.V. 2017. All rights reserved.
Product data sheet Rev. 10 — 24 November 2017 4 of 26
NXP Semiconductors
TJA1042
High-speed CAN transceiver with Standby mode
6. Pinning information
6.1 Pinning
6.2 Pin description
[1] HVSON8 package die supply ground is connected to both the GND pin and the exposed center pad. The
GND pin must be soldered to board ground. For enhanced thermal and electrical performance, it is
recommended that the exposed center pad also be soldered to board ground.
a. TJA1042T: SO8 b. TJA1042T/3: SO8 c. TJA1042TK/3: HVSON8
Fig 2. Pin configuration diagrams
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Table 3. Pin description
Symbol Pin Description
TXD 1 transmit data input
GND 2
[1]
ground supply
V
CC
3 supply voltage
RXD 4 receive data output; reads out data from the bus lines
SPLIT 5 common-mode stabilization output; in TJA1042T version only
V
IO
5 supply voltage for I/O level adapter; in TJA1042T/3 and TJA1042TK/3 versions
only
CANL 6 LOW-level CAN bus line
CANH 7 HIGH-level CAN bus line
STB 8 Standby mode control input
TJA1042 All information provided in this document is subject to legal disclaimers. © NXP N.V. 2017. All rights reserved.
Product data sheet Rev. 10 — 24 November 2017 5 of 26
NXP Semiconductors
TJA1042
High-speed CAN transceiver with Standby mode
7. Functional description
The TJA1042 is a HS-CAN stand-alone transceiver with Standby mode. It combines the
functionality of the PCA82C250, PCA82C251 and TJA1040 transceivers with improved
EMC and ESD handling capability and quiescent current performance. Improved slope
control and high DC handling capability on the bus pins provide additional application
flexibility.
The TJA1042 is available in two versions, distinguished only by the function of pin 5:
The TJA1042T is backwards compatible with the TJA1040 when used with a 5 V
microcontroller, and also covers existing PCA82C250 and PCA82C251 applications
The TJA1042T/3 and TJA1042TK/3 allow for direct interfacing to microcontrollers with
supply voltages down to 3 V
7.1 Operating modes
The TJA1042 supports two operating modes, Normal and Standby, which are selected via
pin STB. See Table 4
for a description of the operating modes under normal supply
conditions.
7.1.1 Normal mode
A LOW level on pin STB selects Normal mode. In this mode, the transceiver can transmit
and receive data via the bus lines CANH and CANL (see Figure 1
for the block diagram).
The differential receiver converts the analog data on the bus lines into digital data which is
output to pin RXD. The slopes of the output signals on the bus lines are controlled
internally and are optimized in a way that guarantees the lowest possible EME.
7.1.2 Standby mode
A HIGH level on pin STB selects Standby mode. In Standby mode, the transceiver is not
able to transmit or correctly receive data via the bus lines. The transmitter and
Normal-mode receiver blocks are switched off to reduce supply current, and only a
low-power differential receiver monitors the bus lines for activity. The wake-up filter on the
output of the low-power receiver does not latch bus dominant states, but ensures that only
bus dominant and bus recessive states that persist longer than t
fltr(wake)bus
are reflected on
pin RXD.
In Standby mode, the bus lines are biased to ground to minimize the system supply
current. The low-power receiver is supplied by V
IO
, and is capable of detecting CAN bus
activity even if V
IO
is the only supply voltage available. When pin RXD goes LOW to signal
a wake-up request, a transition to Normal mode will not be triggered until STB is forced
LOW.
Table 4. Operating modes
Mode Pin STB Pin RXD
LOW HIGH
Normal LOW bus dominant bus recessive
Standby HIGH wake-up request
detected
no wake-up request
detected
TJA1042 All information provided in this document is subject to legal disclaimers. © NXP N.V. 2017. All rights reserved.
Product data sheet Rev. 10 — 24 November 2017 6 of 26
NXP Semiconductors
TJA1042
High-speed CAN transceiver with Standby mode
7.2 Fail-safe features
7.2.1 TXD dominant time-out function
A ‘TXD dominant time-out’ timer is started when pin TXD is set LOW. If the LOW state on
pin TXD persists for longer than t
to(dom)TXD
, the transmitter is disabled, releasing the bus
lines to recessive state. This function prevents a hardware and/or software application
failure from driving the bus lines to a permanent dominant state (blocking all network
communications). The TXD dominant time-out timer is reset when pin TXD is set to HIGH.
The TXD dominant time-out time also defines the minimum possible bit rate of 40 kbit/s.
7.2.2 Bus dominant time-out function
In Standby mode a 'bus dominant time-out' timer is started when the CAN bus changes
from recessive to dominant state. If the dominant state on the bus persists for longer than
t
to(dom)bus
, the RXD pin is reset to HIGH. This function prevents a clamped dominant bus
(due to a bus short-circuit or a failure in one of the other nodes on the network) from
generating a permanent wake-up request. The bus dominant time-out timer is reset when
the CAN bus changes from dominant to recessive state.
7.2.3 Internal biasing of TXD and STB input pins
Pins TXD and STB have internal pull-ups to V
IO
to ensure a safe, defined state in case
one or both of these pins are left floating. Pull-up currents flow in these pins in all states;
both pins should be held HIGH in Standby mode to minimize standby current.
7.2.4 Undervoltage detection on pins V
CC
and V
IO
Should V
CC
drop below the V
CC
undervoltage detection level, V
uvd(VCC)
, the transceiver
will switch to Standby mode. The logic state of pin STB will be ignored until V
CC
has
recovered.
Should V
IO
drop below the V
IO
undervoltage detection level, V
uvd(VIO)
, the transceiver will
switch off and disengage from the bus (zero load) until V
IO
has recovered.
Fig 3. Wake-up timing
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TJA1042T,112

Mfr. #:
Manufacturer:
NXP Semiconductors
Description:
CAN Interface IC CAN 1Mbps Standby 3.3V/5V 8-Pin
Lifecycle:
New from this manufacturer.
Delivery:
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