12
12. The optical rise and fall times are measured from 10% to 90% when
the transmitter is driven by a 25 MBd (12.5 MHz square-wave) input
signal. The ANSI T1E1.2 committee has designated the possibility of
de ning an eye pattern mask for the transmitter optical output as
an item for further study. Avago will incorporate this requirement
into the speci cations for these products if it is de ned. The HFBR-
59XXL products typically comply with the template requirements of
CCITT (now ITU-T) G.957 Section 3.2.5, Figure 5 for the STM- 1 rate,
excluding the optical receiver lter normally associated with single
mode ber measurements which is the likely source for the ANSI
T1E1.2 committee to follow in this matter.
13a. Systematic Jitter contributed by the transmitter is de ned as the
combination of Duty Cycle Distortion and Data Dependent Jitter.
Systematic Jitter is measured at 50% threshold using a 155.52 MBd
(77.5 MHz square-wave), 2
23
-1 psuedorandom data pattern input
signal.
13b. Duty Cycle Distortion contributed by the transmitter is measured at
the 50% threshold of the optical output signal using an IDLE Line
State, 125 MBd (62.5 MHz square-wave), input signal.
13c. Data Dependent Jitter contributed by the transmitter is speci ed
with the FDDI test pattern described in FDDI PMD Annex A.5.
14a. Random Jitter contributed by the transmitter is speci ed with a
155.52 MBd (77.5 MHz square-wave) input signal.
14b. Random Jitter contributed by the transmitter is speci ed with an
IDLE Line State, 125 MBd (62.5 MHz square-wave), input signal. See
Application Information - Transceiver Jitter Performance Section of
this data sheet for further details.
15a. This speci cation is intended to indicate the performance of the
receiver section of the transceiver when Input Optical Power signal
characteristics are present per the At the Beginning of Life (BOL)
over the speci ed operating temperature and voltage ranges 23
input is a 155.52 MBd, 2 - 1 PRBS data pattern with 72 “1” s and
72 “0”s inserted per the CCITT (now ITU-T) recommendation G.958
Appendix I.
Receiver data window time-width is 1.23 ns or greater for the clock
recovery circuit to operate in. The actual test data window time-
width is set to simulate the e ect of worst case optical input jitter
based on the transmitter jitter values from the speci cation tables.
The test window time-width is HFBR-5963L 3.32 ns.
Transmitter operating with a 155.52 MBd, 77.5 MHz square-wave,
input signal to simulate any cross-talk present between the trans-
mitter and receiver sections of the transceiver.
15b. This speci cation is intended to indicate the performance of the
receiver section of the transceiver when Input Optical Power signal
characteristics are present per the following de nitions. The Input
Optical Power dynamic range from the minimum level (with a
window time-width) to the maximum level is the range over which
the receiver is guaranteed to provide output data with a Bit Error
Rate (BER) better than or equal to 2.5 x 10
-10
.
• At the Beginning of Life (BOL)
• Over the speci ed operating temperature and voltage ranges
• Input symbol pattern is the FDDI test pattern de ned in FDDI PMD
Annex A.5 with 4B/5B NRZI encoded data that contains a duty cycle
base-line wander e ect of 50 kHz. This sequence causes a near worst
case condition for inter-symbol interference.
• Receiver data window time-width is 2.13 ns or greater and centered
at mid-symbol. This worst case window time-width is the minimum
allowed eye-opening presented to the FDDI PHY PM_Data indica-
tion input (PHY input) per the example in FDDI PMD Annex E. This
minimum window time-width of 2.13 ns is based upon the worst
case FDDI PMD Active Input Interface optical conditions for peak-
to-peak DCD (1.0 ns), DDJ (1.2 ns) and RJ (0.76 ns) presented to the
receiver.
To test a receiver with the worst case FDDI PMD Active Input jitter
condition requires exacting control over DCD, DDJ and RJ jitter
compo nents that is di cult to implement with production test
equipment. The receiver can be equivalently tested to the worst case
FDDI PMD input jitter conditions and meet the minimum output
data window time-width of 2.13 ns. This is accom plished by using
a nearly ideal input optical signal (no DCD, insigni cant DDJ and
RJ) and measuring for a wider window time-width of 4.6 ns. This is
possible due to the cumula tive e ect of jitter components through
their superposition (DCD and DDJ are directly additive and RJ com-
ponents are rms additive). Speci cally, when a nearly ideal input
optical test signal is used and the maximum receiver peak-to-peak
jitter contributions of DCD (0.4 ns), DDJ (1.0 ns), and RJ (2.14 ns)
exist, the minimum window time-width becomes 8.0 ns -0.4 ns - 1.0
ns - 2.14 ns = 4.46 ns, or conservatively 4.6 ns. This wider window
time-width of 4.6 ns guarantees the FDDI PMD Annex E minimum
window time-width of 2.13 ns under worst case input jitter condi-
tions to the Avago receiver.
• Transmitter operating with an IDLE Line State pattern, 125 MBd (62.5
MHz square-wave), input signal to simulate any cross-talk present
between the trans mit ter and receiver sections of the transceiver.
16a. All conditions of Note 15a apply except that the measurement is
made at the center of the symbol with no window time- width.
16b. All conditions of Note 15b apply except that the measurement is
made at the center of the symbol with no window time-width.
17a. Systematic Jitter contributed by the receiver is de ned as the com-
bination of Duty Cycle Distortion and Data Dependent Jitter. Sys-
tematic Jitter is measured at 50% threshold using a 155.52 MBd
(77.5 MHz square- wave), 2
23
- 1 psuedorandom data pattern input
signal.
17b. Duty Cycle Distortion contributed by the receiver is measured at
the 50% threshold of the electrical output signal using an IDLE Line
State, 125 MBd (62.5 MHz square-wave), input signal. The input
optical power level is -20 dBm average.
17c. Data Dependent Jitter contributed by the receiver is speci ed with
the FDDI DDJ test pattern described in the FDDI PMD Annex A.5. The
input optical power level is -20 dBm average.
18a. Random Jitter contributed by the receiver is speci ed with a 155.52
MBd (77.5 MHz square- wave) input signal.
18b. Random Jitter contributed by the receiver is speci ed with an IDLE
Line State, 125 MBd (62.5 MHz square-wave), input signal. The input
optical power level is at maxi mum “P
IN Min.
(W)”. See Applica tion In-
formation - Transceiver Jitter Section for further information.
19. This value is measured during the transition from low to high levels
of input optical power.
20. This value is measured during the transition from high to low levels
of input optical power. At Signal Detect Deassert, the receiver
outputs Data Out and Data Out Bar go to steady PECL levels High
and Low respectively.
21. The Signal Detect output shall be asserted within 100 us after a step
increase of the Input Optical Power.
22. Signal detect output shall be de-asserted within 100 μs after a step
decrease in the Input Optical Power. At Signal Detect Deassert, the
receiver outputs Data Out and Data Out Bar go to steady PECL levels
High and Low respectively.
23. The HFBR-5963L transceiver complies with the requirements for the
trade-o s between center wavelength, spectral width, and rise/fall
times shown in Figure 7. This gure is derived from the FDDI PMD
standard (ISO/IEC 9314-3 : 1990 and ANSI X3.166 - 1990) per the de-
scription in ANSI T1E1.2 Revision 3. The interpretation of this gure
is that values of Center Wavelength and Spectral Width must lie
along the appropriate Optical Rise/Fall Time curve.
