8
Integrated Silicon Solution, Inc. — www.issi.com —
1-800-379-4774
Rev. C
03/17/06
IS62WV10248BLL ISSI
®
WRITE CYCLE SWITCHING CHARACTERISTICS
(1,2)
(Over Operating Range)
55 ns 70 ns
Symbol Parameter Min. Max. Min. Max. Unit
tWC Write Cycle Time 55 — 70 — ns
tSCS1/tSCS2 CS1/CS2 to Write End 45 — 60 — ns
tAW Address Setup Time to Write End 45 — 60 — ns
tHA Address Hold from Write End 0 — 0 — ns
tSA Address Setup Time 0 — 0 — ns
tPWE
(4)
WE Pulse Width 40 — 50 — ns
tSD Data Setup to Write End 25 — 30 — ns
tHD Data Hold from Write End 0 — 0 — ns
tHZWE
(3)
WE LOW to High-Z Output — 25 — 25 ns
tLZWE
(3)
WE HIGH to Low-Z Output 5 — 5 — ns
Notes:
1. Test conditions assume signal transition times of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0.4V to V
DD-
0.3V and output loading specified in Figure 1.
2. The internal write time is defined by the overlap of CS1 LOW, CS2 HIGH and WE LOW. All signals must be in valid states to
initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the
rising or falling edge of the signal that terminates the write
.
3. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.
4. t
PWE > tHZWE + tSD when OE is LOW.
AC WAVEFORMS
WRITE CYCLE NO. 1 (CS1/CS2 Controlled, OE = HIGH or LOW)
DATA-IN VALID
DATA UNDEFINED
tWC
tSCS1
tSCS2
tAW
tHA
t
PWE
tHZWE
HIGH-Z
tLZWE
tSA
tSD tHD
ADDRESS
CS1
CS2
WE
DOUT
DIN
