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NCV5171EDR2G

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P19
NCV5171, NCV5173
www.onsemi.com
10
Switch Driver and Power Switch
The switch driver receives a control signal from the logic
section to drive the output power switch. The switch is
grounded through emitter resistors (63 mW total) to the
PGND pin. PGND is not connected to the IC substrate so that
switching noise can be isolated from the analog ground.
The peak switching current is clamped by an internal circuit.
The clamp current is guaranteed to be greater than 1.5 A and
varies with duty cycle due to slope compensation.
The power switch can withstand a maximum voltage of
40 V on the collector (V
SW
pin). The saturation voltage of
the switch is typically less than 1 V to minimize power
dissipation.
Short Circuit Condition
When a short circuit condition happens in a boost circuit,
the inductor current will increase during the whole
switching cycle, causing excessive current to be drawn from
the input power supply. Since control ICs don’t have the
means to limit load current, an external current limit circuit
(such as a fuse or relay) has to be implemented to protect the
load, power supply and ICs.
In other topologies, the frequency shift built into the IC
prevents damage to the chip and external components. This
feature reduces the minimum duty cycle and allows the
transformer secondary to absorb excess energy before the
switch turns back on.
Figure 25. Startup Waveforms of Circuit Shown in
the Application Diagram. Load = 400 mA.
I
L
V
OU
T
V
C
V
CC
The NCV5171/73 can be activated by either connecting
the V
CC
pin to a voltage source or by enabling the SS pin.
Startup waveforms shown in Figure 25 are measured in the
boost converter demonstrated in the Application Diagram
on the page 2 of this document. Recorded after the input
voltage is turned on, this waveform shows the various
phases during the power up transition.
When the V
CC
voltage is below the minimum supply
voltage, the V
SW
pin is in high impedance. Therefore,
current conducts directly from the input power source to the
output through the inductor and diode. Once V
CC
reaches
approximately 1.5 V, the internal power switch briefly turns
on. This is a part of the NCV5171/73’s normal operation.
The turn−on of the power switch accounts for the initial
current swing.
When the V
C
pin voltage rises above the threshold, the
internal power switch starts to switch and a voltage pulse can
be seen at the V
SW
pin. Detecting a low output voltage at the
FB pin, the built−in frequency shift feature reduces the
switching frequency to a fraction of its nominal value,
reducing the minimum duty cycle, which is otherwise
limited by the minimum on−time of the switch. The peak
current during this phase is clamped by the internal current
limit.
When the FB pin voltage rises above 0.4 V, the frequency
increases to its nominal value, and the peak current begins
to decrease as the output approaches the regulation voltage.
The overshoot of the output voltage is prevented by the
active pull−on, by which the sink current of the error
amplifier is increased once an overvoltage condition is
detected. The overvoltage condition is defined as when the
FB pin voltage is 50 mV greater than the reference voltage.
COMPONENT SELECTION
Frequency Compensation
The goal of frequency compensation is to achieve
desirable transient response and DC regulation while
ensuring the stability of the system. A typical compensation
network, as shown in Figure 26, provides a frequency
response of two poles and one zero. This frequency response
is further illustrated in the Bode plot shown in Figure 27.
NCV5171/73
Figure 26. A Typical Compensation Network
V
C
GND
C1
R1
C2
The high DC gain in Figure 27 is desirable for achieving
DC accuracy over line and load variations. The DC gain of
a transconductance error amplifier can be calculated as
follows:
Gain
DC
+ G
M
R
O
where:
G
M
= error amplifier transconductance;
R
O
= error amplifier output resistance ≈ 1 MW.
The low frequency pole, f
P1,
is determined by the error
amplifier output resistance and C1 as:
f
P1
+
1
2pC1R
O
NCV5171, NCV5173
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11
The first zero generated by C1 and R1 is:
f
Z1
+
1
2pC1R1
The phase lead provided by this zero ensures that the loop
has at least a 45° phase margin at the crossover frequency.
Therefore, this zero should be placed close to the pole
generated in the power stage which can be identified at
frequency:
f
P
+
1
2pC
O
R
LOAD
where:
C
O
= equivalent output capacitance of the error amplifier
≈120 pF;
R
LOAD
= load resistance.
The high frequency pole, f
P2
, can be placed at the output
filter’s ESR zero or at half the switching frequency. Placing
the pole at this frequency will cut down on switching noise.
The frequency of this pole is determined by the value of C2
and R1:
f
P2
+
1
2pC2R1
One simple method to ensure adequate phase margin is to
design the frequency response with a −20 dB per decade
slope, until unity−gain crossover. The crossover frequency
should be selected at the midpoint between f
Z1
and f
P2
where
the phase margin is maximized.
Figure 27. Bode Plot of the Compensation Network
Shown in Figure 26
Frequency (LOG)
f
P1
Gain (dB)
DC Gain
f
Z1
f
P2
V
SW
Voltage Limit
In the boost topology, V
SW
pin maximum voltage is set by
the maximum output voltage plus the output diode forward
voltage. The diode forward voltage is typically 0.5 V for
Schottky diodes and 0.8 V for ultrafast recovery diodes
V
SW(MAX)
+ V
OUT(MAX)
)V
F
where:
V
F
= output diode forward voltage.
In the flyback topology, peak V
SW
voltage is governed by:
V
SW(MAX)
+ V
CC(MAX)
)(V
OUT
)V
F
) N
where:
N = transformer turns ratio, primary over secondary.
When the power switch turns off, there exists a voltage
spike superimposed on top of the steady−state voltage.
Usually this voltage spike is caused by transformer leakage
inductance charging stray capacitance between the V
SW
and
PGND pins. To prevent the voltage at the V
SW
pin from
exceeding the maximum rating, a transient voltage
suppressor in series with a diode is paralleled with the
primary windings. Another method of clamping switch
voltage is to connect a transient voltage suppressor between
the V
SW
pin and ground.
Magnetic Component Selection
When choosing a magnetic component, one must consider
factors such as peak current, core and ferrite material, output
voltage ripple, EMI, temperature range, physical size and
cost. In boost circuits, the average inductor current is the
product of output current and voltage gain (V
OUT
/V
CC
),
assuming 100% energy transfer efficiency. In continuous
conduction mode, inductor ripple current is
I
RIPPLE
+
V
CC
(V
OUT
*
V
CC
)
(f)(L)(V
OUT)
where:
f = 280 kHz (NCV5171) or 560 kHz (NCV5173).
The peak inductor current is equal to average current plus
half of the ripple current, which should not cause inductor
saturation. The above equation can also be referenced when
selecting the value of the inductor based on the tolerance of
the ripple current in the circuits. Small ripple current
provides the benefits of small input capacitors and greater
output current capability. A core geometry like a rod or
barrel is prone to generating high magnetic field radiation,
but is relatively cheap and small. Other core geometries,
such as toroids, provide a closed magnetic loop to prevent
EMI.
Input Capacitor Selection
In boost circuits, the inductor becomes part of the input
filter, as shown in Figure 29. In continuous mode, the input
current waveform is triangular and does not contain a large
pulsed current, as shown in Figure 28. This reduces the
requirements imposed on the input capacitor selection.
During continuous conduction mode, the peak to peak
inductor ripple current is given in the previous section. As
we can see from Figure 28, the product of the inductor
current ripple and the input capacitor’s effective series
resistance (ESR) determine the V
CC
ripple. In most
applications, input capacitors in the range of 10 mF to 100 mF
with an ESR less than 0.3 W work well up to a full 1.5 A
switch current.
NCV5171, NCV5173
www.onsemi.com
12
V
CC
ripple
Figure 28. Boost Input Voltage and Current
Ripple Waveforms
I
IN
I
L
+
−
Figure 29. Boost Circuit Effective Input Filter
V
CC
C
IN
R
ESR
I
L
I
IN
The situation is different in a flyback circuit. The input
current is discontinuous and a significant pulsed current is
seen by the input capacitors. Therefore, there are two
requirements for capacitors in a flyback regulator: energy
storage and filtering. To maintain a stable voltage supply to
the chip, a storage capacitor larger than 20 mF with low ESR
is required. To reduce the noise generated by the inductor,
insert a 1.0 mF ceramic capacitor between V
CC
and ground
as close as possible to the chip.
Output Capacitor Selection
Figure 30. Typical Output Voltage Ripple
V
OUT
ripp
le
I
L
By examining the waveforms shown in Figure 30, we can
see that the output voltage ripple comes from two major
sources, namely capacitor ESR and the
charging/discharging of the output capacitor. In boost
circuits, when the power switch turns off, I
L
flows into the
output capacitor causing an instant DV = I
IN
× ESR. At the
same time, current I
L
− I
OUT
charges the capacitor and
increases the output voltage gradually. When the power
switch is turned on, I
L
is shunted to ground and I
OUT
discharges the output capacitor. When the I
L
ripple is small
enough, I
L
can be treated as a constant and is equal to input
current I
IN
.
Summing up, the output voltage peak−peak ripple can be
calculated by:
V
OUT(RIPPLE)
+
(I
IN
* I
OUT)
(1 * D)
(C
OUT)
(f)
)
I
OUT
D
(C
OUT
)(f)
) I
IN
ESR
The equation can be expressed more conveniently in
terms of V
CC
, V
OUT
and I
OUT
for design purposes as
follows:
V
OUT(RIPPLE)
+
I
OUT
(V
OUT
* V
CC
)
(C
OUT
)(f)
1
(C
OUT
)(f)
)
(I
OUT
)(V
OUT
)(ESR)
V
CC
The capacitor RMS ripple current is:
I
RIPPLE
+ (I
IN
* I
OUT
)
2
(1 * D))(I
OUT
)
2
(D)
Ǹ
+ I
OUT
V
OUT
* V
CC
V
CC
Ǹ
Although the above equations apply only for boost
circuits, similar equations can be derived for flyback
circuits.
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P19

NCV5171EDR2G

Mfr. #:
Buy NCV5171EDR2G
Manufacturer:
ON Semiconductor
Description:
Switching Voltage Regulators ANA 1.5A 260KHZ BOOST REG
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