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NCV5171EDR2G

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P19
NCV5171, NCV5173
www.onsemi.com
13
Reducing the Current Limit
In some applications, the designer may prefer a lower
limit on the switch current than 1.5 A. An external shunt can
be connected between the V
C
pin and ground to reduce its
clamp voltage. Consequently, the current limit of the
internal power transistor current is reduced from its nominal
value.
The voltage on the V
C
pin can be evaluated with the
equation
V
C
+ I
SW
R
E
A
V
where:
R
E
= 0.063 W, the value of the internal emitter resistor;
A
V
= 5 V/V, the gain of the current sense amplifier.
Since R
E
and A
V
cannot be changed by the end user, the
only available method for limiting switch current below
1.5 A is to clamp the V
C
pin at a lower voltage. If the
maximum switch or inductor current is substituted into the
equation above, the desired clamp voltage will result.
A simple diode clamp, as shown in Figure 31, clamps the
V
C
voltage to a diode drop above the voltage on resistor R3.
Unfortunately, such a simple circuit is not generally
acceptable if V
IN
is loosely regulated.
Figure 31. Current Limiting using a Diode Clamp
V
C
D1
V
CC
R1
V
IN
C2
C1
R2
R3
Another solution to the current limiting problem is to
externally measure the current through the switch using
a sense resistor. Such a circuit is illustrated in Figure 32.
−
+
Figure 32. Current Limiting using a Current Sense
Resistor
V
C
R
SENSE
Q1
V
CC
R1
V
IN
C2
C1
R2
C3
Output
Ground
PGND
AGND
The switch current is limited to
I
SWITCH(PEAK)
+
V
BE(Q1)
R
SENSE
where:
V
BE(Q1)
= the base−emitter voltage drop of Q1, typically
0.65 V.
The improved circuit does not require a regulated voltage
to operate properly. Unfortunately, a price must be paid for
this convenience in the overall efficiency of the circuit. The
designer should note that the input and output grounds are
no longer common. Also, the addition of the current sense
resistor, R
SENSE
, results in a considerable power loss which
increases with the duty cycle. Resistor R2 and capacitor C3
form a low−pass filter to remove noise.
NCV5171, NCV5173
www.onsemi.com
14
Subharmonic Oscillation
Subharmonic oscillation (SHM) is a problem found in
current−mode control systems, where instability results
when duty cycle exceeds 50%. SHM only occurs in
switching regulators with a continuous inductor current.
This instability is not harmful to the converter and usually
does not affect the output voltage regulation. SHM will
increase the radiated EM noise from the converter and can
cause, under certain circumstances, the inductor to emit
high−frequency audible noise.
SHM is an easily remedied problem. The rising slope of
the inductor current is supplemented with internal “slope
compensation” to prevent any duty cycle instability from
carrying through to the next switching cycle. In
NCV5171/73, the slope compensation is added during the
entire switch on−time, typically in the amount of 180 mA/ms.
In some cases, SHM can rear its ugly head despite the
presence of the onboard slope compensation. The simple
cure to this problem is more slope compensation to avoid the
unwanted oscillation. In that case, an external circuit, shown
in Figure 33, can be added to increase the amount of slope
compensation used. This circuit requires only a few
components and is “tacked on” to the compensation
network.
Figure 33. Technique for Increasing Slope
Compensation
V
C
R1
C2
C1
R2
R3
V
SW
C3
V
SW
The dashed box contains the normal compensation
circuitry to limit the bandwidth of the error amplifier.
Resistors R2 and R3 form a voltage divider off of the V
SW
pin. In normal operation, V
SW
looks similar to a square
wave, and is dependent on the converter topology. Formulas
for calculating V
SW
in the boost and flyback topologies are
given in the section “V
SW
Voltage Limit.” The voltage on
V
SW
charges capacitor C3 when the switch is off, causing
the voltage at the V
C
pin to shift upwards. When the switch
turns on, C3 discharges through R3, producing a negative
slope at the V
C
pin. This negative slope provides the slope
compensation.
The amount of slope compensation added by this circuit
is:
DI
DT
+ V
SW
ǒ
R
3
R
2
)R
3
Ǔ
ǒ
1 * e
*(1*D)
R
3
C
3
f
SW
Ǔǒ
f
SW
(1 * D)R
E
A
V
Ǔ
where:
DI/DT = the amount of slope compensation added (A/s);
V
SW
= the voltage at the switch node when the transistor
is turned off (V);
f
SW
= the switching frequency, typically 280 kHz
(NCV5171) or 560 kHz (NCV5173)
D = the duty cycle;
R
E
= 0.063 W, the value of the internal emitter resistor;
A
V
= 5 V/V, the gain of the current sense amplifier.
In selecting appropriate values for the slope compensation
network, the designer is advised to choose a convenient
capacitor, then select values for R2 and R3 such that the
amount of slope compensation added is 100 mA/ms. Then
R2 may be increased or decreased as necessary. Of course,
the series combination of R2 and R3 should be large enough
to avoid drawing excessive current from V
SW
. Additionally,
to ensure that the control loop stability is improved, the time
constant formed by the additional components should be
chosen such that
R
3
C
3
t
1 * D
f
SW
Finally, it is worth mentioning that the added slope
compensation is a tradeoff between duty cycle stability and
transient response. The more slope compensation a designer
adds, the slower the transient response will be, due to the
external circuitry interfering with the proper operation of the
error amplifier.
Soft−Start
Through the addition of an external circuit, a Soft−Start
function can be added to the NCV5171/73 family of
components. Soft−Start circuitry prevents the V
C
pin from
slamming high during startup, thereby inhibiting the
inductor current from rising at a high slope.
NCV5171, NCV5173
www.onsemi.com
15
This circuit, shown in Figure 34, requires a minimum
number of components and allows the Soft−Start circuitry to
activate any time the SS pin is used to restart the converter.
Figure 34. Soft Start
V
C
R1
C2
C1
D2
D1
V
CC
C3
V
IN
SS
SS
Resistor R1 and capacitors C1 and C2 form the
compensation network. At turn on, the voltage at the V
C
pin
starts to come up, charging capacitor C3 through Schottky
diode D2, clamping the voltage at the V
C
pin such that
switching begins when V
C
reaches the V
C
threshold,
typically 1.05 V (refer to graphs for detail over temperature).
V
C
+ V
F(D2)
)V
C3
Therefore, C3 slows the startup of the circuit by limiting
the voltage on the V
C
pin. The Soft−Start time increases with
the size of C3.
Diode D1 discharges C3 when SS is low. If the shutdown
function is not used with this part, the cathode of D1 should
be connected to V
IN
.
Calculating Junction Temperature
To ensure safe operation of NCV5171/73, the designer
must calculate the on−chip power dissipation and determine
its expected junction temperature. Internal thermal
protection circuitry will turn the part off once the junction
temperature exceeds 180°C ± 30°. However, repeated
operation at such high temperatures will ensure a reduced
operating life.
Calculation of the junction temperature is an imprecise
but simple task. First, the power losses must be quantified.
There are three major sources of power loss on the
NCV5171/73:
• biasing of internal control circuitry, P
BIAS
• switch driver, P
DRIVER
• switch saturation, P
SAT
The internal control circuitry, including the oscillator and
linear regulator, requires a small amount of power even
when the switch is turned off. The specifications section of
this datasheet reveals that the typical operating current, I
Q
,
due to this circuitry is 5.5 mA. Additional guidance can be
found in the graph of operating current vs. temperature. This
graph shows that IQ is strongly dependent on input voltage,
V
IN
, and temperature. Then
P
BIAS
+ V
IN
I
Q
Since the onboard switch is an NPN transistor, the base
drive current must be factored in as well. This current is
drawn from the V
IN
pin, in addition to the control circuitry
current. The base drive current is listed in the specifications
as DI
CC
/DI
SW
, or switch transconductance. As before, the
designer will find additional guidance in the graphs. With
that information, the designer can calculate
P
DRIVER
+ V
IN
I
SW
I
CC
DI
SW
D
where:
I
SW
= the current through the switch;
D = the duty cycle or percentage of switch on−time.
I
SW
and D are dependent on the type of converter. In a
boost converter,
I
SW(AVG)
^ I
L
(
AVG
)
D
1
Efficiency
D ^
V
OUT
* V
IN
V
OUT
In a flyback converter,
I
SW(AVG)
^
V
OUT
I
LOAD
V
IN
1
Efficiency
1
D
D ^
V
OUT
V
OUT
)
N
S
N
P
V
IN
The switch saturation voltage, V
(CE)SAT
, is the last major
source of on−chip power loss. V
(CE)SAT
is the
collector−emitter voltage of the internal NPN transistor
when it is driven into saturation by its base drive current. The
value for V
(CE)SAT
can be obtained from the specifications
or from the graphs, as “Switch Saturation Voltage.” Thus,
P
SAT
^ V
(CE)SAT
I
SW
D
Finally, the total on−chip power losses are
P
D
+ P
BIAS
)P
DRIVER
)P
SAT
Power dissipation in a semiconductor device results in the
generation of heat in the junctions at the surface of the chip.
This heat is transferred to the surface of the IC package, but
a thermal gradient exists due to the resistive properties of the
package molding compound. The magnitude of the thermal
gradient is expressed in manufacturers’ data sheets as q
JA
,
or junction−to−ambient thermal resistance. The on−chip
junction temperature can be calculated if q
JA
, the air
temperature near the surface of the IC, and the on−chip
power dissipation are known.
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P19

NCV5171EDR2G

Mfr. #:
Buy NCV5171EDR2G
Manufacturer:
ON Semiconductor
Description:
Switching Voltage Regulators ANA 1.5A 260KHZ BOOST REG
Lifecycle:
New from this manufacturer.
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