13
FN9143.5
The modulator transfer function is the small-signal transfer
function of V
OUT
/V
E/A
. This function is dominated by a DC
Gain and the output filter (L
O
and C
O
), with a double pole
break frequency at F
LC
and a zero at F
ESR
. The DC Gain of
the modulator is simply the input voltage (V
IN
) divided by the
peak-to-peak oscillator voltage ΔV
OSC
.
Modulator Break Frequency Equations
The compensation network consists of the error amplifier
(internal to the ISL6537A) and the impedance networks Z
IN
and Z
FB
. The goal of the compensation network is to provide
a closed loop transfer function with the highest 0dB crossing
frequency (f
0dB
) and adequate phase margin. Phase margin
is the difference between the closed loop phase at f
0dB
and
180 degrees. The equations below relate the compensation
network’s poles, zeros and gain to the components (R
1
, R
2
,
R
3
, C
1
, C
2
, and C
3
) in Figure 3. Use these guidelines for
locating the poles and zeros of the compensation network:
1. Pick Gain (R
2
/R
1
) for desired converter bandwidth.
2. Place 1
ST
Zero Below Filter’s Double Pole (~75% F
LC
).
3. Place 2
ND
Zero at Filter’s Double Pole.
4. Place 1
ST
Pole at the ESR Zero.
5. Place 2
ND
Pole at Half the Switching Frequency.
6. Check Gain against Error Amplifier’s Open-Loop Gain.
7. Estimate Phase Margin - Repeat if Necessary.
Compensation Break Frequency Equations
Figure 4 shows an asymptotic plot of the DC/DC converter’s
gain vs. frequency. The actual Modulator Gain has a high gain
peak due to the high Q factor of the output filter and is not
shown in Figure 4. Using the above guidelines should give a
Compensation Gain similar to the curve plotted. The open
loop error amplifier gain bounds the compensation gain.
Check the compensation gain at F
P2
with the capabilities of
the error amplifier. The Closed Loop Gain is constructed on
the graph of Figure 4 by adding the Modulator Gain (in dB) to
the Compensation Gain (in dB). This is equivalent to
multiplying the modulator transfer function to the
compensation transfer function and plotting the gain.
The compensation gain uses external impedance networks
Z
FB
and Z
IN
to provide a stable, high bandwidth (BW) overall
loop. A stable control loop has a gain crossing with
-20dB/decade slope and a phase margin greater than 45
degrees. Include worst case component variations when
determining phase margin.
Output Voltage Selection
The output voltage of all the external voltage regulators can
be programmed to any level between their individual input
voltage and the internal reference, 0.8V. An external resistor
divider is used to scale the output voltage relative to the
reference voltage and feed it back to the inverting input of the
error amplifier, refer to the Typical Application on page 4.
The output voltage programming resistor will depend on the
value chosen for the feedback resistor and the desired
output voltage of the particular regulator.
If the output voltage desired is 0.8V, simply route the output
voltage back to the respective FB pin through the feedback
resistor and do not populate the output voltage programming
resistor.
The output voltage for the internal V
TT_DDR
linear regulator
is set internal to the ISL6537A to track the V
DDQ
voltage by
50%. There is no need for external programming resistors.
F
LC
1
2π x L
O
x C
O
-------------------------------------------= F
ESR
1
2π x ESR x C
O
--------------------------------------------=
(EQ. 4)
F
Z1
1
2π x R
2
x C
1
------------------------------------=
F
Z2
1
2π x R
1
R
3
+() x C
3
-------------------------------------------------------=
F
P1
1
2π x R
2
x
C
1
x C
2
C
1
C
2
+
----------------------
⎝⎠
⎜⎟
⎛⎞
---------------------------------------------------------=
F
P2
1
2π x R
3
x C
3
------------------------------------=
(EQ. 5)
100
80
60
40
20
0
-20
-40
-60
F
P1
F
Z2
10M1M100K10K1K10010
OPEN LOOP
ERROR AMP GAIN
F
Z1
F
P2
20LOG
F
LC
F
ESR
COMPENSATION
GAIN (dB)
FREQUENCY (Hz)
GAIN
20LOG
(V
IN
/ΔV
OSC
)
MODULATOR
GAIN
(R
2
/R
1
)
FIGURE 4. ASYMPTOTIC BODE PLOT OF CONVERTER GAIN
CLOSED LOOP
GAIN
R4
R1 0.8V×
V
DDQ
0.8V
-----------------------------------=
R8
R5 0.8V×
V
GMCH
0.8V
----------------------------------------=
R10
R9 0.8V×
V
xxxxxxxxxxxx
0.8V
-----------------------------------------------------------=
R12
R11 0.8V×
V
DAC
0.8V
----------------------------------=
TT_GMCH/CPU
(EQ. 6)
ISL6537A
14
FN9143.5
Component Selection Guidelines
Output Capacitor Selection - PWM Buck Converter
An output capacitor is required to filter the inductor current
and supply the load transient current. The filtering
requirements are a function of the switching frequency and
the ripple current. The load transient requirements are a
function of the slew rate (di/dt) and the magnitude of the
transient load current. These requirements are generally met
with a mix of capacitors and careful layout.
DDR memory systems are capable of producing transient
load rates above 1A/ns. High frequency capacitors initially
supply the transient and slow the current load rate seen by the
bulk capacitors. The bulk filter capacitor values are generally
determined by the ESR (Effective Series Resistance) and
voltage rating requirements rather than actual capacitance
requirements.
High frequency decoupling capacitors should be placed as
close to the power pins of the load as physically possible. Be
careful not to add inductance in the circuit board wiring that
could cancel the usefulness of these low inductance
components. Consult with the manufacturer of the load on
specific decoupling requirements.
Use only specialized low-ESR capacitors intended for
switching-regulator applications for the bulk capacitors. The
bulk capacitor’s ESR will determine the output ripple voltage
and the initial voltage drop after a high slew-rate transient. An
aluminum electrolytic capacitor’s ESR value is related to the
case size with lower ESR available in larger case sizes.
However, the Equivalent Series Inductance (ESL) of these
capacitors increases with case size and can reduce the
usefulness of the capacitor to high slew-rate transient loading.
Unfortunately, ESL is not a specified parameter. Work with
your capacitor supplier and measure the capacitor’s
impedance with frequency to select a suitable component. In
most cases, multiple electrolytic capacitors of small case size
perform better than a single large case capacitor.
Output Capacitor Selection - LDO Regulators
The output capacitors used in LDO regulators are used to
provide dynamic load current. The amount of capacitance
and type of capacitor should be chosen with this criteria in
mind.
Output Inductor Selection
The output inductor is selected to meet the output voltage
ripple requirements and minimize the converter’s response
time to the load transient. The inductor value determines the
converter’s ripple current and the ripple voltage is a function
of the ripple current. The ripple voltage and current are
approximated by the following equations:
Increasing the value of inductance reduces the ripple current
and voltage. However, the large inductance values reduce
the converter’s response time to a load transient.
One of the parameters limiting the converter’s response to
a load transient is the time required to change the inductor
current. Given a sufficiently fast control loop design, the
ISL6537A will provide either 0% or 100% duty cycle in
response to a load transient. The response time is the time
required to slew the inductor current from an initial current
value to the transient current level. During this interval the
difference between the inductor current and the transient
current level must be supplied by the output capacitor.
Minimizing the response time can minimize the output
capacitance required.
The response time to a transient is different for the
application of load and the removal of load. The following
equations give the approximate response time interval for
application and removal of a transient load:
where: I
TRAN
is the transient load current step, t
RISE
is the
response time to the application of load, and t
FALL
is the
response time to the removal of load. The worst case
response time can be either at the application or removal of
load. Be sure to check both of these equations at the
minimum and maximum output levels for the worst case
response time.
Input Capacitor Selection - PWM Buck Converter
Use a mix of input bypass capacitors to control the voltage
overshoot across the MOSFETs. Use small ceramic
capacitors for high frequency decoupling and bulk capacitors
to supply the current needed each time the upper MOSFET
turns on. Place the small ceramic capacitors physically close
to the MOSFETs and between the drain of upper MOSFET
and the source of lower MOSFET.
The important parameters for the bulk input capacitance are
the voltage rating and the RMS current rating. For reliable
operation, select bulk capacitors with voltage and current
ratings above the maximum input voltage and largest RMS
current required by the circuit. Their voltage rating should be
at least 1.25 times greater than the maximum input voltage,
while a voltage rating of 1.5 times is a conservative
guideline. For most cases, the RMS current rating
requirement for the input capacitor of a buck regulator is
approximately 1/2 the DC load current.
The maximum RMS current required by the regulator may be
closely approximated through the following equation:
ΔI =
V
IN
- V
OUT
Fs x L
V
OUT
V
IN
ΔV
OUT
= ΔI x ESR
x
(EQ. 7)
t
RISE
=
L x I
TRAN
V
IN
- V
OUT
t
FALL
=
L x I
TRAN
V
OUT
(EQ. 8)
I
RMS
MAX
V
OUT
V
IN
--------------
I
OUT
MAX
2
1
12
------
V
IN
V
OUT
Lf
s
×
-----------------------------
V
OUT
V
IN
--------------
×
⎝⎠
⎛⎞
2
×+
⎝⎠
⎛⎞
×=
(EQ. 9)
ISL6537A
15
FN9143.5
For a through hole design, several electrolytic capacitors
may be needed. For surface mount designs, solid tantalum
capacitors can be used, but caution must be exercised with
regard to the capacitor surge current rating. These
capacitors must be capable of handling the surge-current at
power-up. Some capacitor series available from reputable
manufacturers are surge current tested.
MOSFET Selection - PWM Buck Converter
The ISL6537A requires 2 N-Channel power MOSFETs for
switching power and a third MOSFET to block backfeed from
V
DDQ
to the Input in S3 Mode. These should be selected
based upon r
DS(ON)
, gate supply requirements, and thermal
management requirements.
In high-current applications, the MOSFET power dissipation,
package selection and heatsink are the dominant design
factors. The power dissipation includes two loss
components; conduction loss and switching loss. The
conduction losses are the largest component of power
dissipation for both the upper and the lower MOSFETs.
These losses are distributed between the two MOSFETs
according to duty factor. The switching losses seen when
sourcing current will be different from the switching losses
seen when sinking current. When sourcing current, the
upper MOSFET realizes most of the switching losses. The
lower switch realizes most of the switching losses when the
converter is sinking current (see the equations below).
These equations assume linear voltage-current transitions
and do not adequately model power loss due the reverse-
recovery of the upper and lower MOSFET’s body diode. The
gate-charge losses are dissipated in part by the ISL6537A
and do not significantly heat the MOSFETs. However, large
gate-charge increases the switching interval, t
SW
which
increases the MOSFET switching losses. Ensure that both
MOSFETs are within their maximum junction temperature at
high ambient temperature by calculating the temperature
rise according to package thermal-resistance specifications.
A separate heatsink may be necessary depending upon
MOSFET power, package type, ambient temperature and air
flow.
MOSFET Selection - LDO
The main criteria for selection of the linear regulator pass
transistor is package selection for efficient removal of heat.
Select a package and heatsink that maintains the junction
temperature below the rating with a maximum expected
ambient temperature.
The power dissipated in the linear regulator is:
where I
O
is the maximum output current and V
OUT
is the
nominal output voltage of the linear regulator.
P
LOWER
= Io
2
x r
DS(ON)
x (1 - D)
Where: D is the duty cycle = V
OUT
/V
IN
,
t
SW
is the combined switch ON and OFF time, and
f
s
is the switching frequency.
Approximate Losses while Sourcing current
Approximate Losses while Sinking current
P
LOWER
Io
2
r
DS ON()
× 1D()×
1
2
---
Io V
IN
× t
SW
f
s
××+=
P
UPPER
Io
2
r
DS ON()
× D×
1
2
---
Io V
IN
× t
SW
f
s
××+=
P
UPPER
= Io
2
x r
DS(ON)
x D
(EQ. 10)
P
LINEAR
I
O
V
IN
V
OUT
()×
(EQ. 11)
ISL6537A

ISL6537ACRZ-TR5160

Mfr. #:
Manufacturer:
Renesas / Intersil
Description:
Switching Controllers SPECIAL METAL OPTION FOR VREF
Lifecycle:
New from this manufacturer.
Delivery:
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