4
FN9143.5
Simplified Power System Diagram
Typical Application
PWM
5VSBY
VTT
ISL6537A
CONTROLLER
REGULATOR
12V
V
REF
V
TT
+
SLEEP
STATE
LOGIC
SLP_S3
SLP_S5
Q5
+
3V3ATX
V
DDQ
Q1
5VDUAL
Q2
+
V
TT_GMCH/CPU
LINEAR
CONTROLLER
V
GMCH
Q4
Q3
LINEAR
CONTROLLER
Q6
+
V
DAC
INTERSIL
FET DRIVER
PWM
CONTROLLER
+
3V3ATX
5VSBY
ISL6537A
FB4
GND
V
GMCH
5VSBY
P12V
SLP_S5
SLP_S3
S5#
S3#
12V
ATX3V3
DRIVE2
FB2
V
TT_GMCH/CPU
VIDPGD
PWM4
COMP4
INTERSIL
FET DRIVER
DRIVE3
FB3
V
DAC
UGATE
FB
COMP
LGATE
DDR_VTT(x2)
V
TT_DDR
VREF_IN
VREF_OUT
DDR_VTTSNS
V
DDQ_DDR
+
5VDUAL
OCSET
PHASE
V
REF
DDR_VDDQ(x2)
BOOT
Q2
Q1
Q3
Q4
Q5
Q6
R
OCSET
R1
R2
C1
C2
R3
C3
R4
R5
C5
R6
C6
R7
C7
R8
R9
R10
R9
R12
R11
3VDUAL
D
BOOT
C
BOOT
ATX3V3
ISL6537A
5
FN9143.5
Absolute Maximum Ratings Thermal Information
5VSBY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .GND - 0.3V to +7V
P12V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .GND - 0.3V to +14V
Absolute Boot Voltage, V
BOOT
. . . . . . . . . . . . . . . . . . . . . . . +15.0V
Upper Driver Supply Voltage, V
BOOT
- V
PHASE
. . . . . . . . 7.0V (DC)
8.0V (<10ns Pulse Width, 10μJ)
All other Pins . . . . . . . . . . . . . . . . . . . . GND - 0.3V to 5VCC + 0.3V
ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 2
Recommended Operating Conditions
Supply Voltage on 5VSBY . . . . . . . . . . . . . . . . . . . . . . . . +5V ±10%
Supply Voltage on P12V . . . . . . . . . . . . . . . . . . . . . . . . +12V ±10%
Ambient Temperature Range. . . . . . . . . . . . . . . . . . . . 0°C to +70°C
Junction Temperature Range. . . . . . . . . . . . . . . . . . . 0°C to +125°C
Thermal Resistance (Typical, Notes 1, 2)
θ
JA
(°C/W) θ
JC
(°C/W)
QFN Package . . . . . . . . . . . . . . . . . . . 32 5
Maximum Junction Temperature (Plastic Package) . . . . . . +150°C
Maximum Storage Temperature Range. . . . . . . . . -65°C to +150°C
Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and
result in failures not covered by warranty.
NOTES:
1. θ
JA
is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See
Tech Brief TB379.
2. For θ
JC
, the “case temp” location is the center of the exposed metal pad on the package underside.
Electrical Specifications Recommended Operating Conditions, Unless Otherwise Noted. Refer to Block and Simplified Power System
Diagrams and Typical Application Schematics
PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS
5VSBY SUPPLY CURRENT
Nominal Supply Current I
CC_S0
S3# and S5# HIGH, UGATE/LGATE Open 5.5 7.0 8.0 mA
I
CC_S5
S5# LOW, S3# Don’t Care, UGATE/LGATE Open - 700 850 μA
POWER-ON RESET
Rising 5VSBY POR Threshold 4.10 - 4.45 V
Falling 5VSBY POR Threshold 3.60 - 3.95 V
Rising P12V POR Threshold 10.0 - 10.5 V
Falling P12V POR Threshold 8.80 - 9.75 V
OSCILLATOR AND SOFT-START
PWM Frequency f
OSC
220 250 280 kHz
Ramp Amplitude ΔV
OSC
-1.5- V
Soft-Start Interval t
SS
6.5 8.2 9.5 ms
REFERENCE VOLTAGE
Reference Voltage V
REF
-0.800- V
System Accuracy -2.0 - +2.0 %
V
DDQ
AND V
GMCH
PWM CONTROLLER ERROR AMPLIFIERS
DC Gain (Note 3) - 80 - dB
Gain-Bandwidth Product GBWP (Note 3) 15 - - MHz
Slew Rate SR (Note 3) - 6 - V/μs
CONTROL I/O (S3#, S5#)
LOW Level Input Threshold 0.75 - - V
HIGH Level Input Threshold --2.2V
ISL6537A
6
FN9143.5
Functional Pin Description
5VSBY (Pin 1)
5VSBY is the bias supply of the ISL6537A. It is typically
connected to the 5V standby rail of an ATX power supply.
During S4/S5 sleep states the ISL6537A enters a reduced
power mode and draws less than 1mA (I
CC_S5
) from the
5VSBY supply. The supply to 5VSBY should be locally
bypassed using a 0.1μF capacitor.
P12V (Pin 3)
The V
TT
regulation circuit and the Linear Drivers are
powered by P12V. P12V is not required during S3/S4/S5
operation. P12V is typically connected to the +12V rail of an
ATX power supply.
GND (Pins 4, 27, 29)
The GND terminals of the ISL6537A provide the return path
for the V
TT
LDO, and switching MOSFET gate drivers. High
PWM CONTROLLER GATE DRIVERS
UGATE and LGATE Source I
GATE
--0.8- A
UGATE and LGATE Sink I
GATE
-0.8- A
VTT REGULATOR
Upper Divider Impedance R
U
-2.5- kΩ
Lower Divider Impedance R
L
-2.5- kΩ
VREF_OUT Buffer Source Current I
VREF_OUT
--2mA
Maximum V
TT
Load Current I
VTT_MAX
Periodic load applied with 30% duty cycle and
10ms period using ISL6537A_6506EVAL1
evaluation board (see Application Note AN1124)
-3 - 3 A
LINEAR REGULATORS
DC Gain (Note 3) - 80 - dB
Gain Bandwidth Product GBWP (Note 3) 15 - - MHz
Slew Rate SR (Note 3) - 6 - V/μs
DRIVEn High Output Voltage DRIVEn Unloaded 9.75 10.0 - V
DRIVEn Low Output Voltage -0.160.50 V
DRIVEn High Output Source Current V
FB
= 770mV, V
DRIVEn
= 0V - 1.7 - mA
DRIVEn Low Output Sink Current V
FB
= 830mV, V
DRIVEn
= 10V - 1.20 - mA
VIDPGD
V
TT_GMCH/CPU
Rising Threshold S0 .725 .740 - V
V
TT_GMCH/CPU
Falling Threshold S0 - 0.700 0.715 V
PROTECTION
OCSET Current Source I
OCSET
18 20 22 μA
V
TT_DDR
Current Limit (Note 3) -3.3 - 3.3 A
V
DDQ
OV Level V
FB
/V
REF
S0/S3 - 115 - %
V
DDQ
UV Level V
FB
/V
REF
S0/S3 - 75 - %
V
TT_DDR
OV Level V
TT
/V
VREF_IN
S0 - 115 - %
V
TT_DDR
UV Level V
TT
/V
VREF_IN
S0 - 85 - %
V
GMCH
UV Level V
FB4
/V
REF
S0 - 75 - %
V
TT_GMCH/CPU
UV Level V
FB2
/V
REF
S0 - 75 - %
Thermal Shutdown Limit T
SD
(Note 3) - 140 - °C
NOTE:
3. Limits should be considered typical and are not production tested
Electrical Specifications Recommended Operating Conditions, Unless Otherwise Noted. Refer to Block and Simplified Power System
Diagrams and Typical Application Schematics (Continued)
PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS
ISL6537A

ISL6537ACRZ-TR5160

Mfr. #:
Manufacturer:
Renesas / Intersil
Description:
Switching Controllers SPECIAL METAL OPTION FOR VREF
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
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