ADM1025/ADM1025A
Preliminary Technical Data
Rev. P5 | Page 16 of 21| www.onsemi.com
3. The device whose
INT
output is low responds to the Alert
Response Address, and the master reads its device address.
The address of the device is now known and it can be
interrogated in the usual way.
4.
If more than one devices
INT
output is low, the one with
the lowest device address will have priority, in accordance
with normal SMBus arbitration.
5.
Once the ADM1025/ADM1025A has responded to the
Alert Response Address, it will reset its
INT
output;
however, if the error condition that caused the interrupt
persists,
INT
will be reasserted on the next monitoring
cycle.
NAND TREE TESTS
A NAND tree is provided in the ADM1025/ADM1025A for
Automated Test Equipment (ATE) board level connectivity
testing. The device is placed into NAND Test Mode by
powering up with Pin 9 (D-/NTI) held high. This pin is
automatically sampled after power-up, and if it is connected
high, the NAND test mode is invoked.
In NAND test mode, all digital inputs may be tested as
illustrated below. ADD/
RST
/
INT
/NTO will become the NAND
test output pin.
To perform a NAND tree test, all pins are initially driven low.
The test vectors set all inputs low, then one-by-one toggle them
high (keeping them high). Exercising the test circuit with this
“walking one” pattern, starting with the input closest to the
output of the tree, cycling toward the farthest, causes the output
of the tree to toggle with each input change. Allow for a typical
propagation delay of 500 ns. The structure of the NAND tree is
shown in Figure 18.
Figure 18. NAND Tree
Note: If any of the inputs shown in Figure 18 are unused, they
should not be connected directly to ground but via a resistor
such as 10 kΩ. This will allow the ATE to drive every input high
so that the NAND tree test can be properly carried out. Refer to
Table 19 for Test Vectors.
Preliminary Technical Data
ADM1025/ADM1025A
Rev. P5 | Page 17 of 21| www.onsemi.com
USING THE ADM1025/ADM1025A
POWER-ON RESET
When power is first applied, the ADM1025/ADM1025A
performs a “power- on reset” on several of its registers.
Registers whose power-on values are not shown have power-on
conditions that are indeterminate. Value and limit registers are
reset to 00h on power-up. The ADC is inactive. In most
applications, usually the first action after power-on would be to
write limits into the Limit Registers.
Power-on reset clears or initializes the following registers (the
initialized values are shown in Table 9):
– Configuration Register
– Status Registers #1 and #2
– VID0-3 Register
– VID4 Register
– Test Register
INITIALIZATION
Configuration Register Initialization performs a similar, but not
identical, function to power-on reset.
Configuration Register Initialization is accomplished by setting
Bit 7 of the Configuration Register high. This bit automatically
clears after being set.
USING THE CONFIGURATION REGISTER
Control of the ADM1025/ADM1025A is provided through the
configuration register. The Configuration Register is used to
start and stop the ADM1025/ADM1025A, program the
operating modes of Pins 11 and 16, and provide the
initialization function described above.
Bit 0 of the Configuration Register controls the monitoring loop
of the ADM1025/ADM1025A. Setting Bit 0 low stops the
monitoring loop and puts the ADM1025/ADM1025A into a
low power mode thereby reducing power consumption. Serial
bus communication is still possible with any register in the
ADM1025/ADM1025A while in low power mode. Setting Bit 0
high starts the monitoring loop.
Bit 4 of the Configuration Register causes a low going 20 ms
(typ) pulse at the
RST
pin (Pin 16) when set. This bit is self-
clearing.
Bit 5 of the Configuration Register selects the operating mode
of Pin 11 between the default of 12 V analog input (Bit 5 = 0)
and VID4 (Bit 5 = 1).
Bit 7 of the Configuration Register is used to start a
Configuration Register Initialization when it is set to 1.
USING THE OFFSET REGISTER
This register contains a twos complement value that is added
(or subtracted if the number is negative) to either the internal
or external temperature reading. Note that the default value in
the offset register is zero, so zero is always added to the
temperature reading. The offset register is configured for the
external temperature channel by default. It may be switched to
the internal channel by setting Bit 0 of the Test Register to 1,
setting Bit 6 of the VID Register to 1, and clearing Bit 7 of the
VID Register.
STARTING CONVERSION
The monitoring function of the ADM1025/ADM1025A is
started by writing to the Configuration Register and setting
Start (Bit 0) high. Limit values should be written into the Limit
Registers before starting the ADC to avoid spurious out-of-limit
conditions. The time taken to complete the analog
measurements depends on how they are configured, as
described elsewhere. Once the measurements have been
completed, the results can be read from the Value Registers at
any time.
REDUCED POWER AND SHUTDOWN MODE
The ADM1025/ADM1025A can be placed in a low power mode
by setting Bit 0 of the Configuration Register to 0. This disables
the internal ADC. Full shutdown mode may then be achieved
by setting Bit 7 of the VID Register to 1 and Bit 0 of the Test
Register to 1. This turns off power to all analog circuits and
stops the monitoring cycle, if running, but it does not affect the
condition of any of the registers. The device will return to its
previous state when these bits are reset to zero.
5 V OPERATION
The ADM1025/ADM1025A may be operated with V
CC
connected to any supply voltage between 3.0 V and 5.5 V, but it
should be noted that the device has been optimized for 3.3 V
operation. In particular, the internal voltage divider used to
measure the supply voltage is optimized for 3.3 V. Powering the
device from 5 V will cause the V
CC
Reading Register (Register
25h) to overrange. In this case, the 5 V measurement should be
read from the 5 V Reading Register (Register 23h), instead of
the V
CC
Reading Register. Note also that when the 12 V
IN
/VID4
pin is programmed to read VID4, due to its internal voltage
divider, it will only read V
IH
= 2.1 V on the 12 V
IN
/VID4 pin as
logic high if the device is being powered from the 3.3 V supply.
ADM1025/ADM1025A
Preliminary Technical Data
Rev. P5 | Page 18 of 21| www.onsemi.com
REGISTERS
Table 8. Address POINTER Register
Bit Name R/
W
Description
7–0 Address Pointer Write Address of ADM1025/
ADM1025A Registers. See
the tables below for detail.
Table 9. List of Registers
Register Name
Address
A7–A0
in Hex
Power On Value of
Registers: <7:0>
Configuration
Register
40h 0000 1000
Status Register 1 41h 0000 0000
Status Register 2 42h 0000 0000
VID Register 47h <7:4> = 0000, <3:0> = VID3–
VID0
VID4 Register 49h <0> = VID4; Default = 1000
000 (VID4)
Value and Limit
Registers
15–3Dh
Company ID 3Eh 0100 0001
Stepping 3Fh 0010 (Bits 3:0 Version
Number)
Table 10. Register 40h – Configuration Register
Bit Name R/
W
Description
0 START Read/Write Logic 1 enables startup of
monitor ASIC, and Logic 0
places the ASIC in standby
mode. At startup, limit
checking functions and
scanning begins. Note, all
HIGH and LOW LIMITS should
be set into the ADM1025/
ADM1025A prior to turning
on this bit. (Power-up Default
= 0.)
1 Reserved Read
2 Reserved Read
3 Reserved Read
4 RESET Read/Write Setting this bit generates a
minimum 20 ms low pulse on
Pin 16 if the function is
enabled.
5 +12/VID4
Select
Read/Write Selects whether Pin 11 acts
as a 12 V analog input
monitoring pin, or as a VID[4]
input. This pin defaults to the
12 V analog input. (Default =
0.)
6 Reserved Read
7 Initialization Read/Write Logic 1 restores power-up
default values to the
Configuration Register and
Status Registers. This bit
automatically clears itself and
the power-on default is zero.

ADM1025ARQZ

Mfr. #:
Manufacturer:
ON Semiconductor
Description:
IC MONITOR SYS/VOLT 5CH 16QSOP
Lifecycle:
New from this manufacturer.
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