NCV7321
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6
with a reverse−protection diode is internally connected
between LIN and V
BB
pins.
To avoid that, due to a failure of the application (e.g.
software error), the LIN bus is permanently driven dominant
and thus blocking all subsequent communication, signal on
pin TxD passes through a timer, which releases the bus in
case TxD remains low for longer than T_TxD_timeout. The
transmission can continue once the TxD returns to High
logical level.
In case the junction temperature increases above the
thermal shutdown threshold, e.g. due to a short of the LIN
wiring to the battery, the transmitter is disabled and releases
LIN bus to recessive. Once the junction temperature
decreases back below the thermal shutdown release level,
the transmission can be enabled again – however, to avoid
thermal oscillations, first a High logical level on TxD must
be encountered before the transmitter is enabled.
As required by SAE J2602, the transceiver must behave
safely below its operating range – it shall either continue to
transmit correctly (according its specification) or remain
silent (transmit a recessive state regardless of the TxD
signal). A battery monitoring circuit in NCV7321
de−activates the transmitter in the normal mode if the V
BB
level drops below MONL_V
BB
. Transmission is enabled
again when V
BB
reaches MONH_V
BB
. The internal logic
remains in the normal mode and the reception from the LIN
line is still possible even if the battery monitor disables the
transmission. Although the specifications of the monitoring
and power−on−reset levels are overlapping, it’s ensured by
the implementation that the monitoring level never falls
below the power−on−reset level.
Normal mode can be entered from either standby or sleep
mode when EN Pin is High for longer than T_enable. When
the transition is made from standby mode, TxD pull−down
is set to weak and RxD is put high−impedant immediately
after EN becomes High (before the expiration of T_enable
filtering time). This excludes signal conflicts between the
standby mode pin settings and the signals required to control
the chip in the normal mode (e.g. strong pull−down on TxD
after local wake−up vs. High logical level on TxD required
to send a recessive symbol on LIN).
Sleep Mode
Sleep mode provides extremely low current consumption.
The LIN transceiver is inactive and the battery consumption
is minimized. Pin INH is put to high−impedant state to
disable the external regulator and, in case of a master node,
the LIN termination – see Figure 2. Only a weak pull−up
current source is internally connected between LIN and
V
BB
Pins, in order to minimize current consumption even in
case of LIN short to GND.
Sleep mode can be entered from normal mode by
assigning Low logical level to pin EN for longer than
T_disable. The sleep mode can be entered even if a
permanent short occurs either on LIN or WAKE Pin.
If a wake−up event occurs during the transition between
normal and sleep mode (during the T_disable filtering time),
it will be regarded as valid wake−up and the chip will enter
standby mode with the appropriate setting of Pins RxD and
TxD.
Wake−up
Two types of wake−up events are recognized by NCV7321:
• Local wake−up – when a high−to−low transition on pin
WAKE is encountered and WAKE pin remains Low at
least during T_WAKE – see Figure 4.
• Remote (or LIN) wake−up – when LIN bus is
externally driven dominant during longer than
T_LIN_wake and a rising edge on LIN occurs
afterwards – see Figure 5.
Wake−up events can be exclusively detected in sleep mode
or during the transition from normal mode to sleep mode.
Due to timing tolerances, valid wake−up events beginning
shortly before normal−to−sleep mode transition can be also
sometimes regarded as valid wake−ups.
WAKE
t
V
BB
Local Wake−up recognized
Sleep Mode Standby Mode
V_WAKE_th
T_WAKE
Figure 4. Local Wake−up Detection
