3-CHANNEL HIGH-PERFORMANCE TCXO/LVCMOS CLOCK BUFFER FAMILY 4 FEBRUARY 28, 2018
5PB12xx DATASHEET
DC Electrical Characteristics
(VDD = 1.8V, 2.5V, 3.3V)
VDD = 1.8V ±5%, for 5PB1203 / 1204 / 1206, ambient temperature -40° to +105°C, unless stated otherwise.
VDD = 2.5V ±5%, for 5PB1213 / 1214 / 1216, ambient temperature -40° to +105°C, unless stated otherwise.
Parameter Symbol Conditions Min. Typ. Max. Units
Operating Voltage VDD 1.71 1.89 V
Input High Voltage, CLKIN V
IH
LVCMOS input. Note 1 VDD/2 + 200 VDD mV
Input Low Voltage, CLKIN V
IL
LVCMOS input. Note 1 VDD/2 - 200 mV
Input High Voltage, OE V
IH
0.7xVDD VDD V
Input Low Voltage, OE V
IL
0.3xVDD V
Output High Voltage V
OH
I
OH
= -4mA 0.8xVDD V
Output Low Voltage V
OL
I
OL
= 4mA 0.2xVDD V
Nominal Output Impedance Z
O
17
Input Capacitance C
IN
5pF
Operating Supply Current
5PB1203
IDD
CLKIN = 26MHz, all outputs enabled 5.10
mA
CLKIN = Low or High, all outputs disabled 0.02 0.03
5PB1204
CLKIN = 26MHz, all outputs enabled 9.30
CLKIN = Low or High, all outputs disabled 2.51 4
5PB1206
CLKIN = 26MHz, all outputs enabled 11.90
CLKIN = Low or High, all outputs disabled 2.5 4
Parameter Symbol Conditions Min. Typ. Max. Units
Operating Voltage VDD 2.375 2.625 V
Input High Voltage, CLKIN V
IH
LVCMOS input. Note 1 VDD/2 + 200 VDD mV
Input Low Voltage, CLKIN V
IL
LVCMOS input. Note 1 VDD/2 - 200 mV
Input High Voltage, OE V
IH
0.7xVDD VDD V
Input Low Voltage, OE V
IL
0.3xVDD V
Output High Voltage V
OH
I
OH
= -4mA 0.8xVDD V
Output Low Voltage V
OL
I
OL
= 4mA 0.2xVDD V
Nominal Output Impedance Z
O
17
Input Capacitance C
IN
ICLK, OE pin 5 pF
Operating Supply Current
5PB1213
IDD
CLKIN = 26MHz, all outputs enabled 6.68
mA
CLKIN = Low or High, all outputs disabled 0.05 0.5
5PB1214
CLKIN = 26MHz, all outputs enabled 10.2
CLKIN = Low or High, all outputs disabled 3.47 5
5PB1216
CLKIN = 26MHz, all outputs enabled 16.5
CLKIN = Low or High, all outputs disabled 3.50 5
FEBRUARY 28, 2018 5 3-CHANNEL HIGH-PERFORMANCE TCXO/LVCMOS CLOCK BUFFER FAMILY
5PB12xx DATASHEET
VDD = 3.3V ±5%, for 5PB1213 / 1214 / 1216, ambient temperature -40° to +105°C, unless stated otherwise
Notes: 1. Nominal switching threshold is VDD/2.
Parameter Symbol Conditions Min. Typ. Max. Units
Operating Voltage VDD 3.135 3.465 V
Input High Voltage, CLKIN V
IH
LVCMOS input. Note 1 VDD/2 + 200 VDD mV
Input Low Voltage, CLKIN V
IL
LVCMOS input. Note 1 VDD/2 - 200 mV
Input High Voltage, OE V
IH
0.7xVDD VDD V
Input Low Voltage, OE V
IL
0.3xVDD V
Output High Voltage V
OH
I
OH
= -4mA 0.8xVDD V
Output Low Voltage V
OL
I
OL
= 4mA 0.2xVDD V
Nominal Output Impedance Z
O
17
Input Capacitance C
IN
ICLK, OE pin 5 pF
Operating Supply Current
5PB1213
IDD
CLKIN = 26MHz, all outputs enabled 9.10
mA
CLKIN = Low or High, all outputs disabled 0.22 0.5
5PB1214
CLKIN = 26MHz, all outputs enabled 13.4
CLKIN = Low or High, all outputs disabled 4.28 7
5PB1216
CLKIN = 26MHz, all outputs enabled 21.4
CLKIN = Low or High, all outputs disabled 4.60 7
3-CHANNEL HIGH-PERFORMANCE TCXO/LVCMOS CLOCK BUFFER FAMILY 6 FEBRUARY 28, 2018
5PB12xx DATASHEET
AC Electrical Characteristics
(VDD = 1.8V, 2.5V, 3.3V)
VDD = 1.8V ±5%; for 5PB1203 / 1204 / 1206, ambient Temperature -40° to +105°C, unless stated otherwise
VDD = 2.5V ±5%; for 5PB1213 / 1214 / 1216, ambient Temperature -40° to +105°C, unless stated otherwise
Parameter Symbol Conditions Min. Typ. Max. Units
Input Frequency 0 200 MHz
Output Rise Time t
OR
0.36 to 1.44V, C
L
= 5pF 0.6 1.0 ns
Output Fall Time t
OF
1.44 to 0.36V, C
L
= 5pF 0.6 1.0 ns
Propagation Delay Note 1 Note 1 1.5 2.0 2.5 ns
Buffer Additive Phase Jitter, RMS 26MHz TCXO clipped sine wave input,
Integration Range: 12kHz to 20MHz
420 fs
125MHz LVCMOS input,
Integration Range: 12kHz to 20MHz
42 fs
Output to Output Skew t
SKEWOO
Note 2, Rising edges at VDD/2 20 50 ps
Device to Device Skew t
SKEWD-D
Rising edges at VDD/2 200 ps
Delay for Output Enable / Disable
Time ENABLEx to BCLKn
t
EN/
t
DIS
CL < 5pF 3 cycles
Start-up Time t
START-UP
2ms
TCXO Clock Clipped Sine Wave
Input Voltage Swing Level
VIN
pp
VDD = 1.8V, should connect to CLKIN
through AC coupling and bias circuit
0.8 V
Parameter Symbol Conditions Min. Typ. Max. Units
Input Frequency 0 200 MHz
Output Rise Time t
OR
0.5 to 2.0V, C
L
= 5pF 0.6 1.0 ns
Output Fall Time t
OF
2.0 to 0.5V, C
L
= 5pF 0.6 1.0 ns
Propagation Delay Note 1 Note 1 1.7 2.2 2.7 ns
Buffer Additive Phase Jitter, RMS 26MHz TCXO clipped sine wave input,
Integration Range: 12kHz to 20MHz
280 fs
125MHz LVCMOS input,
Integration Range: 12kHz to 20MHz
30 fs
Output to Output Skew t
SKEWOO
Note 2, Rising edges at VDD/2 20 50 ps
Device to Device Skew t
SKEWD-D
Rising edges at VDD/2 200 ps
Delay for Output Enable / Disable
Time ENABLEx to BCLKn
t
EN/
t
DIS
CL < 5pF 3 cycles
Start-up Time t
START-UP
Part start-up time for valid outputs after
VDD ramp-up
2ms
TCXO Clock Clipped Sine Wave
Input Voltage Swing Level
VIN
pp
VDD = 2.5V, should connect to CLKIN
through AC coupling and bias circuit
0.8 V

5PB1206NDGK8

Mfr. #:
Manufacturer:
IDT
Description:
Clock Buffer 5PB1206 Mixed Signal
Lifecycle:
New from this manufacturer.
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