13
FN8248.4
October 16, 2015
ENDURANCE AND DATA RETENTION
CAPACITANCE
POWER-UP TIMING
Power-up and Power-down Requirements
There are no restrictions on the power-up or power-down
conditions of V
CC
and the voltage applied to the
potentiometer pins provided that V
CC
is always more
positive than or equal to V
H
, V
L
, and V
W
, i.e., V
CC
V
H
, V
L
,
V
W
. The V
CC
ramp rate spec is always in effect.
AC Test Conditions
Equivalent AC Load Circuit
Circuit #3 SPICE Macro Model
I
LO
Output Leakage Current V
OUT
= V
SS
to V
CC
10 µA
V
IH
Input HIGH Voltage V
CC
x 0.7 V
CC
x 0.5 V
V
IL
Input LOW Voltage -0.5 V
CC
x 0.1 V
V
OL
Output LOW voltage I
OL
= 3mA 0.4 V
SYMBOL PARAMETER TEST CONDITIONS
LIMITS
MIN.
(Note 7) TYP
MAX.
(Note 7) UNIT
PARAMETER MIN. UNIT
Minimum Endurance 100,000 Data changes per bit per register
Data Retention 100 Years
SYMBOL TEST TYP UNIT TEST CONDITIONS
C
I/O
(Note 5) Input/output capacitance (SDA) 8 pF V
I/O
= 0V
C
IN
(Note 5) Input capacitance (A0, A2,and A3 and SCL) 6 pF V
IN
= 0V
SYMBOL PARAMETER MIN TYP MAX UNIT
t
R
V
CC
(Note 6) V
CC
Power-up ramp rate 0.2 50 V/ms
NOTES:
1. Absolute linearity is utilized to determine actual wiper voltage versus expected voltage as determined by wiper position when used as a
potentiometer.
2. Relative linearity is utilized to determine the actual change in voltage between two successive tap positions when used as a potentiometer. It is
a measure of the error in step size.
3. MI = RTOT/63 or (R
H
- R
L
)/63, single pot
4. Typical = individual array resolutions.
5. Limits established by characterization and are not production tested.
6. Sample tested only.
7. Parts are 100% tested at +25°C. Over temperature limits established by characterization and are not production tested.
Input pulse levels V
CC
x 0.1 to V
CC
x 0.9
Input rise and fall times 10ns
Input and output timing level V
CC
x 0.5
5V
1533
100pF
SDA OUTPUT
2.7V
100pF
10pF
R
H
R
TOTAL
C
H
25pF
C
W
C
L
10pF
R
W
R
L
X9429
