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PHD38N02LT,118

P1-P3P4-P6P7-P9P10-P12P13-P13
Important notice
Dear Customer,
On 7 February 2017 the former NXP Standard Product business became a new company with the
tradename Nexperia. Nexperia is an industry leading supplier of Discrete, Logic and PowerMOS
semiconductors with its focus on the automotive, industrial, computing, consumer and wearable
application markets
In data sheets and application notes which still contain NXP or Philips Semiconductors references, use
the references to Nexperia, as shown below.
Instead of http://www.nxp.com, http://www.philips.com/ or http://www.semiconductors.philips.com/,
use http://www.nexperia.com
Instead of sales.addresses@www.nxp.com or sales.addresses@www.semiconductors.philips.com, use
salesaddresses@nexperia.com (email)
Replace the copyright notice at the bottom of each page or elsewhere in the document, depending on
the version, as shown below:
- © NXP N.V. (year). All rights reserved or © Koninklijke Philips Electronics N.V. (year). All rights
reserved
Should be replaced with:
- © Nexperia B.V. (year). All rights reserved.
If you have any questions related to the data sheet, please contact our nearest sales office via e-mail
or telephone (details via salesaddresses@nexperia.com). Thank you for your cooperation and
understanding,
Kind regards,
Team Nexperia
1. Product profile
1.1 General description
Logic level N-channel enhancement mode Field-Effect Transistor (FET) in a plastic
package using TrenchMOS technology.
1.2 Features
1.3 Applications
n Linear regulator for Double-Data Rate (DDR) memory
1.4 Quick reference data
2. Pinning information
[1] It is not possible to make a connection to pin 2.
PHD38N02LT
N-channel TrenchMOS logic level FET
Rev. 02 — 2 February 2007 Product data sheet
n Low on-state resistance n 2.5 V gate drive
n V
DS
≤ 20 V n I
D
≤ 44.7 A
n R
DSon
≤ 16 mΩ n P
tot
≤ 57.6 W
Table 1. Pinning
Pin Description Simplified outline Symbol
1 gate (G)
SOT428 (DPAK)
2 drain (D)
[1]
3 source (S)
mb mounting base; connected to drain (D)
3
2
mb
1
S
D
G
mbb076
PHD38N02LT_2 © NXP B.V. 2007. All rights reserved.
Product data sheet Rev. 02 — 2 February 2007 2 of 12
NXP Semiconductors
PHD38N02LT
N-channel TrenchMOS logic level FET
3. Ordering information
4. Limiting values
Table 2. Ordering information
Type number Package
Name Description Version
PHD38N02LT DPAK plastic single-ended surface-mounted package; 3 leads
(one lead cropped)
SOT428
Table 3. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol Parameter Conditions Min Max Unit
V
DS
drain-source voltage 25 °C ≤ T
j
≤ 175 °C - 20 V
V
DGR
drain-gate voltage (DC) 25 °C ≤ T
j
≤ 175 °C; R
GS
=20kΩ -20V
V
GS
gate-source voltage - ±12 V
I
D
drain current T
mb
=25°C; V
GS
= 5 V; see Figure 2 and 3 - 44.7 A
T
mb
= 100 °C; V
GS
= 5 V; see Figure 2 - 31.6 A
I
DM
peak drain current T
mb
=25°C; pulsed; t
p
≤ 10 µs; see Figure 3 - 179 A
P
tot
total power dissipation T
mb
=25°C; see Figure 1 - 57.6 W
T
stg
storage temperature −55 +175 °C
T
j
junction temperature −55 +175 °C
Source-drain diode
I
S
source current T
mb
=25°C - 44.7 A
I
SM
peak source current T
mb
=25°C; pulsed; t
p
≤ 10 µs - 179 A
P1-P3P4-P6P7-P9P10-P12P13-P13

PHD38N02LT,118

Mfr. #:
Buy PHD38N02LT,118
Manufacturer:
Nexperia
Description:
MOSFET TAPE13 MOSFET
Lifecycle:
New from this manufacturer.
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