26
LTC2401/LTC2402
APPLICATIO S I FOR ATIO
WUUU
ANTIALIASING
One of the advantages delta-sigma ADCs offer over con-
ventional ADCs is on-chip digital filtering. Combined with
a large oversampling ratio, the LTC2401/LTC2402 signifi-
cantly simplify antialiasing filter requirements.
The digital filter provides very high rejection except at
integer multiples of the modulator sampling frequency
(f
S
), see Figure 26. The modulator sampling frequency is
256 • F
O
, where F
O
is the notch frequency (typically 50Hz
or 60Hz). The bandwidth of signals not rejected by the
digital filter is narrow (≈0.2%) compared to the bandwidth
of the frequencies rejected.
As a result of the oversampling ratio (256) and the digital
filter, minimal (if any) antialias filtering is required in front
of the LTC2401/LTC2402. If passive RC components are
placed in front of the LTC2401/LTC2402, the input dy-
namic current should be considered (see Input Current
section). In cases where large effective RC time constants
are used, an external buffer amplifier may be required to
minimize the effects of input dynamic current.
The modulator contained within the LTC2401/LTC2402
can handle large-signal level perturbations without satu-
rating. Signal levels up to 40% of V
REF
do not saturate the
analog modulator. These signals are limited by the input
ESD protection to 300mV below ground and 300mV above
V
CC
.
Single Ended Half-Bridge Digitizer
with Reference and Ground Sensing
Sensors convert real world phenomena (temperature,
pressure, gas levels, etc.) into a voltage. Typically, this
voltage is generated by passing an excitation current
through the sensor. The wires connecting the sensor to
the ADC form parasitic resistors R
P1
and R
P2
. The excita-
tion current also flows through parasitic resistors R
P1
and
R
P2
, as shown in Figure 27. The voltage drop across these
parasitic resistors leads to systematic offset and full-scale
errors.
In order to eliminate the errors associated with these
parasitic resistors, the LTC2401/LTC2402 include a full-
scale set input (FS
SET
) and a zero-scale set input
(ZS
SET
). As shown in Figure 28, the FS
SET
pin acts as a zero
current full-scale sense input. Errors due to parasitic
resistance R
P1
in series with the half-bridge sensor are
removed by the FS
SET
input to the ADC. The absolute full-
scale output of the ADC (data out = FFFFFF
HEX
) will occur
INPUT FREQUENCY
0
–60
–40
0
24012 F26
–80
–100
f
S
/2 f
S
–120
–140
–20
REJECTION (dB)
Figure 26. Sinc
4
Filter Rejection
V
FULL-SCALE ERROR
SENSOR SENSOR OUTPUT
R
P1
I
EXCITATION
+
–
V
OFFSET ERROR
+
–
+
–
R
P2
24012 F27
V
CC
LTC2401
FS
SET
GND
SCK
V
IN
SDO
F
O
CS
ZS
SET
3-WIRE
SPI INTERFACE
1
9
8
7
10
24012 F03
2
3
5
R
P2
R
P5
I
DC
= 0
R
P1
V
B
V
A
6
R
P4
I
DC
= 0
I
EXCITATION
R
P3
I
DC
= 0
Figure 28. Half-Bridge Digitizer with
Zero-Scale and Full-Scale Sense
Figure 27. Errors Due to Excitation Currents
