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9DB403DGILFT

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P19
IDT
®
Four Output Differential Buffer for PCIe Gen 1 and Gen 2 ICS9DB403D REV R 11/1/12
ICS9DB403D
Four Output Differential Buffer for PCIe for Gen 1 and Gen 2
10
Vdiff Vp-p Vcm R1 R2 R3 R4 Note
0.45v 0.22v 1.08 33 150 100 100
0.58 0.28 0.6 33 78.7 137 100
0.80 0.40 0.6 33 78.7 none 100 ICS874003i-02 input compatible
0.60 0.3 1.2 33 174 140 100 Standard LVDS
R1a = R1b = R1
R2a = R2b = R2
Alternative Termination for LVDS and other Common Differential Signals (figure 3)
HCSL Output Buffer
L1
L1'
R1b
L2
L2'
R1a
L4'
L4
L3
R2a R2b
Down Device
REF_CLK Input
Figure 3
L3'
R3 R4
Component Value Note
R5a, R5b 8.2K 5%
R6a, R6b 1K 5%
Cc 0.1 µF
Vcm 0.350 volts
Cable Connected AC Coupled Application (figure 4)
PCIe Device
REF_CLK Input
Figure 4
R5a
L4'
L4
3.3 Volts
R5b
R6a R6b
Cc
Cc
IDT
®
Four Output Differential Buffer for PCIe Gen 1 and Gen 2 ICS9DB403D REV R 11/1/12
ICS9DB403D
Four Output Differential Buffer for PCIe for Gen 1 and Gen 2
11
General SMBus serial interface information for the ICS9DB403D
How to Write:
• Controller (host) sends a start bit.
• Controller (host) sends the write address DC
(h)
• ICS clock will
acknowledge
• Controller (host) sends the begining byte location = N
• ICS clock will
acknowledge
• Controller (host) sends the data byte count = X
• ICS clock will
acknowledge
• Controller (host) starts sending
Byte N through
Byte N + X -1
• ICS clock will
acknowledge
each byte
one at a time
• Controller (host) sends a Stop bit
How to Read:
• Controller (host) will send start bit.
• Controller (host) sends the write address DC
(h)
• ICS clock will
acknowledge
• Controller (host) sends the begining byte
location = N
• ICS clock will
acknowledge
• Controller (host) will send a separate start bit.
• Controller (host) sends the read address DD
(h)
• ICS clock will
acknowledge
• ICS clock will send the data byte count = X
• ICS clock sends
Byte N + X -1
• ICS clock sends
Byte 0 through byte X (if X
(h)
was written to byte 8)
.
• Controller (host) will need to acknowledge each byte
• Controllor (host) will send a not acknowledge bit
• Controller (host) will send a stop bit
ICS (Slave/Receiver)
T
WR
ACK
ACK
ACK
ACK
ACK
PstoP bit
X Byte
Index Block Write Operation
Slave Address DC
(h)
Beginning Byte = N
WRite
starT bit
Controller (Host)
Byte N + X - 1
Data Byte Count = X
Beginning Byte N
T starT bit
WR WRite
RT Repeat starT
RD ReaD
Beginning Byte N
Byte N + X - 1
N Not acknowledge
PstoP bit
Slave Address DD
(h)
Index Block Read Operation
Slave Address DC
(h)
Beginning Byte = N
ACK
ACK
Data Byte Count = X
ACK
ICS (Slave/Receiver)
Controller (Host)
X Byte
ACK
ACK
IDT
®
Four Output Differential Buffer for PCIe Gen 1 and Gen 2 ICS9DB403D REV R 11/1/12
ICS9DB403D
Four Output Differential Buffer for PCIe for Gen 1 and Gen 2
12
SMBus Table: Frequency Select Register, READ/WRITE ADDRESS (DC/DD)
Pin # Name Control Function T
yp
e 0 1 Defaul
t
Bit 7
PD_Mode PD# drive mode RW driven Hi-Z 0
Bit 6
STOP_Mode DIF_Stop# drive mode RW driven Hi-Z 0
Bit 5
Reserved Reserved RW X
Bit 4
Reserved Reserved RW X
Bit 3
Reserved Reserved RW X
Bit 2
PLL_BW# Select PLL BW RW High BW Low BW 1
Bit 1
BYPASS# BYPASS#/PLL RW fan-out ZDB 1
Bit 0
SRC_DIV# SRC Divide by 2 Select RW x/2 1x 1
SMBus Table: Output Control Register
Pin # Name Control Function T
yp
e 0 1 Defaul
t
Bit 7
Reserved Reserved RW 1
Bit 6
DIF_6 Output Enable RW Disable Enable 1
Bit 5
DIF_5 Output Enable RW Disable Enable 1
Bit 4
Reserved Reserved RW 1
Bit 3
Reserved Reserved RW 1
Bit 2
DIF_2 Output Enable RW Disable Enable 1
Bit 1
DIF_1 Output Enable RW Disable Enable 1
Bit 0
Reserved Reserved RW 1
NOTE:
The SMBus Output Enable Bit must be '1' AND the respective OE pin must be active for the output to run!
SMBus Table: OE Pin Control Register
Pin # Name Control Function T
yp
e 0 1 Defaul
t
Bit 7
Reserved Reserved RW 0
Bit 6
DIF_6 DIF_6 Stoppable with DIFSTOP RW Free-run Stoppable 0
Bit 5
DIF_5 DIF_5 Stoppable with DIFSTOP RW Free-run Stoppable 0
Bit 4
Reserved Reserved RW 0
Bit 3
Reserved Reserved RW 0
Bit 2
DIF_2 DIF_2 Stoppable with DIFSTOP RW Free-run Stoppable 0
Bit 1
DIF_1 DIF_1 Stoppable with DIFSTOP RW Free-run Stoppable 0
Bit 0
Reserved Reserved RW 0
SMBus Table: Reserved Register
Pin # Name Control Function T
yp
e 0 1 Defaul
t
Bit 7
X
Bit 6
X
Bit 5
X
Bit 4
X
Bit 3
X
Bit 2
X
Bit 1
X
Bit 0
X
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
- Reserved
-
-
-
B
y
te 2
-
-
9,10
-
22,23
Reserved
Reserved
-
B
y
te 1
-
22,23
Reserved
6,7
19,20
9.1
-
-
B
y
te 0
-
-
-
-
19,20
6,7
-
B
y
te 3
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P19

9DB403DGILFT

Mfr. #:
Buy 9DB403DGILFT
Manufacturer:
IDT
Description:
Clock Buffer 4-output Differential Buffer For PCIe Gen1-2
Lifecycle:
New from this manufacturer.
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